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Recent content by mmic1978

  1. M

    What is the relation between the dead zone of phase detector and the jitter ?

    pll design problem thanks all for share your experience
  2. M

    Question about the switch cap in VCO design

    good discussion
  3. M

    how to simulate phase noise of vco in Simulink

    Re: wo finde ich vco simulink you can build a freq counter, and calcu the delta to get the period and c-c jitter
  4. M

    About Simulink model for Charge Pump PLL.

    thanks, it is very cool
  5. M

    Looking for PLL examples and designs created using Simulink

    plls and simulink it is very well for sharing FracN pll also need modeling
  6. M

    DIVIDE A CLOCK BY 2.5

    good share, thank you
  7. M

    The procedure of the simulation of the Harmonic Distortion

    Re: The procedure of the simulation of the Harmonic Distorti in cadence calculator, use dB20 fuc to plot your DFT results that is dB20(DFT("V(.... good luck~~
  8. M

    PLL RF synthesizer - question with covering the UHF band

    LC VCO just use switching cap array 1. band with switching 2. tuning with vtune the problem is the variation of Kvco
  9. M

    How to reduce the phase noise of a ring VCO

    Current mirror bias maybe degrad PN about 10dB Use large L and design more overdrive voltage for current mirror bias
  10. M

    How can I get Gm for a MOSFET in ADS?

    you must get some sense before your design gm is the transconductance, just use to descrip the Ids v.s. Vgs! so did simulation use dive...
  11. M

    how the charge pump output current convert to voltage?

    just use the sink and source current to charge and discharge the Cap! PFD detect the width of pulse to control the sink and source time~~
  12. M

    How to use calculator to plot the VCO gain,

    1. if you use PSS, sweeppss for the vtune and plot the harmonic 1 freq~ 2. if you use Tran, just get a Eqn like frequency(V(Fvco)) use calculator, then para sweep the vtune good luck!
  13. M

    Latest RF tutorial uploaded

    so great job~~! thank you very much, it is very useful for self-teching Best Regards.
  14. M

    Design of wb synthesizer (3-7G)

    I think so, maybe it is -126dBc/Hz@1MHz Best Regards.
  15. M

    some question on my VCO tuning curve!!!

    if you change the symmetric load as NMOS and use PMOS tail curent bias , you will get the normal positive VCO tuning curve~~ By the way: you Kvco about 1GHz/V, it is so large for Phase noise!
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