What is the relation between the dead zone of phase detector and the jitter ?

[jerryhuang]

what is the relation between the dead zone of phase detector and the jitter , spur ,bandwith of the pll? thx!

 

[khouly]

Re: pll design problem

the dead zone is the phase difference that can't be detected by the phase detector
so this will make the pll will not lock exactly on the phase so , it will pass a jetter "phase noise"

spur noise is mainly the noise due to perodic comparisson in phase detector
this will modulate the vco with the refference frequcny so the band width of the pll will control the atteneuation of spur frequncy

khouly

 

[rfsystem]

Re: pll design problem

Not only deadzone is critical but any nonlinearity. If the PLL is fractional modulated the nonlinearity introduce noise folding from high frequency to low frequency. So the noise frequency shaping is less effective. In some cases the folded back noise around the PLL corner frequency could be higher than the noise current of the chargepump.

 

[amarnath]

pll design problem

i understand thatd dead zone is nothing but.when the phase difference between the reference and the vco output becomes less than that of the delay throught the pfd(phase freq detector),then naturally the pfd cannot send any update pulses.so this results in a dead zone.dead zone leads to jitter because ,in this zone,the pfd does not respond to the phase difference and it makes the vco accumulate as much random phase as possible.now i have a question ,how to simulate dead zone of pll in cadence.please explain in detail.also i need to do a phase noise analysis of my pll.how could i do it with spectre in cadence.i do not want to do a behavioral model analysis by writing a verilog a model.

regards
amarnath

 

[rfsystem]

Re: pll design problem

The source is not only accumulation of jitter. You can think of bouncing between the ends of the deadzone. The nonlinearity is mainly defined by the ratio of the current rise and fall times to the minimum active from the phase frequency detector. If the charge pump and the phase/frequency detector is CMOS there is also temperature, process and supply tracking. So the minimum reset delay time in the detector could be setup reletive to the rise/fall time of the chargepump.

Added after 11 minutes:

The most appropiate tool is Matlab or C to simulate millions of reference cycles. Because of the noisy nature you need 10k reference cyles at e.g 10MHz and average them over 100. At the Spice domain with the VCO there is no chance to investigate low frequency noise problems.

 

[khouly]

Re: pll design problem

simply to simulate the deadzone , "i donot know cadence well"
but sweep the phase difference between the two sources
and plot the phase difference VS the mean output current for charge pump
this will lead u to the famous response of the tristate pfd and u can see the dead zone
i think there is a example in @DS show this very well

khouly

 

[amarnath]

pll design problem

hello rfsystem,u seem to be knowning some good facts.can u tell me how to simulate phase noise of vco in cadence.

 

[hanm]

Re: pll design problem

Simulation phase noise of vco is simple,you need setup PSS plus Pnoise analysis in cadence simulation envirment.If you don't know how to do it ,just have a look at cadence's cdsdoc. Good luck.

 

[layes2]

Re: pll design problem

jitter=1/Tdead zone/Tclk*foutput

 

[Firas]

Re: pll design problem

Phase noise and jitter are different ways of quantifying the same phenomenon. In the ideal world, the duration of a perfectly pulsed signal at a certain frequency level – 1 MHz, for instance – would be exactly 1 μs, with an alternating edge every 500 ns. Such a signal, unfortunately, does not exist. As shown in Figure 1, there are bound to be variations in the length of the period, which causes uncertainty about when the next edge of the signal will occur. This uncertainty is phase noise or jitter.

 

[dinesh agarwal]

pll design problem

dead zone is the result of no response from the osc when the phase diff is less.

the sesign of PFD can eliminate it

if the pulse width of the control voltage to osc is too wide when the phase diff is zero this may lead to high jitter without notice

 

[layes2]

pll design problem

dead zone add jitter

Added after 1 minutes:

also phase nosie

 

[mmic1978]

pll design problem

thanks all for share your experience