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Recent content by mkrishnap

  1. M

    help in system verilog

    Deepu_s_s, In total, the signals in the interface are connected to one or the other module & no signal is kept unconnected. Then how do you say that they left unconnected? We will be using different instances of the same interface and use the signals whichever are required for that particular...
  2. M

    pci express verification

    If you are well versed with PCIe, then you yourself will know the differences. The basic thing is - PCI is parallel bus protocol where as PCIe is serial. So the test-bench will have to be modified for many feature changes. And there are lot many....
  3. M

    How to update output port in two process

    Hi, Won't the modified code of master_picengineer below work...?? ENTITY clk_event IS ....... ....... rise:process begin if (clk'event and (clk = '1' or clk = '0')) then temp <= din; end if; end process; dout <= temp; END ARCHITECTURE clk_event; -mkrishnap
  4. M

    pci express verification

    starting pcie verification Hi balasub, I don't think any one here can help you regarding this. It is purely PCI & PCIE protocol related, and can't be listed here. You need to study the protocol and find the enhancements/differences. If the question is mre directed, I can give it a try. Let me...
  5. M

    event construct in verilog BFM

    Hi asicengineer1, The “event” construct is simple in verilog. Only two operators are used, “->” for triggering and “@” for waiting the event to trigger. Both of the operators can be used in any of the initial or always blocks. See the following counter example, where an always block will...
  6. M

    Discussion on two importat constructs in system verilog

    Hi Satish, The folowing PPT will be helpful for beginers in SV. Anyways, if you 're proficient in verilog & C, understandnig the SV concepts is not a big deal...But how to utilise them in the real-time projects...is more important... www.systemverilog.org/pdf/SV_Symposium_2003.pdf -mkrishnap
  7. M

    Discussion on two importat constructs in system verilog

    Deepak, The key-words “unique” and “priority” are part of the SV language, used with if-else/case statements. They are not only the directives for synthesis tool, as in Verilog. The “unique” is replacement for “parallel_case” and “priority” is replacement for “full_case” synthesis directives...
  8. M

    What are Circular FIFO & Ping-Pong FIFO?

    circular fifo Hi, There are many discussions related to FIFO depth calculation in this site. But I couldn't find any detailed explanation for Circular/Ping-Pong (varieties of FIFO) here. Any description of these will be very helpful. Regards, mkrishnap

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