Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
You need to choose compatible Linux distro so that it will work nicely with your laptop hardware.
Instead of dual-boot, you can also install it in virtual machine like vmware or virtualbox, this way you can access your linux in window ( including vista ) and share files.
Re: Open Access & DFII
With OpenAccess database you can write C++ programs to extract data from the database instead of using proprietary Cadence Skill codes. Many EDA tools start to support OA data format. This means for example you can use same C++ program to access database generated by...
reading an excel file to c++
You can use Excel's Save As to XML Spreadsheet. This dump the content of excel to xml in text. Then you can use public library to read the xml data.
Re: questions about systemc
(1) Is it possible to call C-function from SystemC code.
Yes, SystemC is based on C++ which is based on C.
(2) Is it possible to co-simulate C-code with SystemC code.
What do you want to simulate with the C-code? SystemC has a kernel that manages concurrency to...
You can use AstroRail for static analysis. It's a garbage-in-garbage-out tool, can be painful to debug. Support both flat and hierarchical analysis for big design. Performance wise, flat analysis is good enough for block level but fullchip is an issue for 65nm and beyond.
Hi all,
I'm new to Virtuoso and layout in general. I have a hierarchical cell and I want to flatten it. By doing so can I match metal name one-to-one in the hierachical cell and the flatten cell? Example is something like this
HierarchicalTopCell
-> Cell Instance 1
-> Cell Instance 2...
systemc on windows using devc
I've tried with Bloodshed's Dev C++ IDE. It's an open source version of VC++. Dev C++ can import VC++ workspace file (*.dsw). So you can execute compilation after that. It works.
Hi Omara007,
One tool, Forte Cynthesizer, got good reviews from companies in Japan. You can read it all on deepchip. But Forte Cynthesizer is mostly for datapath and it is more of a behavioural synthesis tool. Prosilog also has a SystemC to VHDL tool. In terms of maturity, Forte is the one.
Hi omara007,
I agree with you. It is total waste of effort. Remember that each rewrite require verification and validation again.
The problem is the lack or non-existent of logic synthesis tool for RTL SystemC ( yes guys, SystemC do support RTL coding not only system level ). The Synopsys's...
Re: Job in USA
Several months before 9/11, I got my H1B visa approved. It's stamped nicely in my passport. The thing is I never managed to step foot in US. The company that paid for my H1B visa spend more than USD5K for it but they didn't called me to go and actually work there. They just say...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
