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schematic simulation
I design LNA schematic. For modeling I use extracted model in chip schematic + pkg model + models external capacitors and inductors. In some nets I use tline3 created in LMG GUI.
1) How I can create model of my external PCB design and modeling in Cadence IC ?
2) Which...
rf pcb
I design LNA schematic. For modeling I use extracted model in chip schematic + pkg model + models external capacitors and inductors. In some nets I use tline3 created in LMG GUI.
1) How I can create model of my external PCB design and modeling in Cadence IC ?
2) Which utilites i...
hspice dac
what models of devices you use? Are you have models with statistical? You can set number points on lineary changing signal and see M and sigma in Monte-carlo analisys.
CT SD ADC
I think a basic limiting factor there is unideality of components: key, opamp ;noise in MOS, CAP, RES; unideality C(V) character capacitance; you can get more than 20 bit of monotony but not linear.
I'm sorry. When project start, system was need in 10bit, but from little time we stoped on 9 bit quality. This code for differential 9-bit SAR, logic have 2 8b register N,P for drive par of key on res ladder.
sar adcs basics
When I design ADC (any type) for algoritm or logic I use verilog code. And for SAR you mast have not only 1 reg. Your logic bloc must contain driver for S/H, driver for Comparator and DAC. Realize this functions in primitive logic components not use VERILOG is difficult.
nyquist sampling frequency criteria
relations between bit rate max IF sampling and other values you can find in book "CMOS sample and hold circuits for high speed A/D conversion" Kok Chin Chang 1991
Chose of architecture depend from accuracy, sampling rate, Vpp, technology. You can find number papers which describe different architectures. For slow sample and high resolution you can chose opamp based schemes, for high speed applications best solutions is SEF and diode bridge based schemes.
Re: how understand phase
Phase margin is a measure of stability your circuit. If phase margin not enought great, you will have oscillatory process on unit step.
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