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output impedance of current mirror in hspice
Hi LvM,
I used the method that you told.using Hspice to sim:
for example:
i0 out 0 0.5u ac=1(0.5ua is static point, through tran simulation)
If change the 0.5uA to 0.50001uA(because of process change), the output impandence will change a lot.
When simulation the output impandence,
there is a big difference output impandence when use difference static bias current to simulation the output impandence?
I used the OP feedback to increase the output impandence.
Because the parasitical capacitance.
refer to "SFDR-BANDWITH LIMITATIONS FOR HIGH SPEED HIGH RESOLUTION CURRENT STEERING COMS D/A CONVERTERS"
BTW: I have a question , there is a big difference output impandence when use difference static bias current to simulation the output impandence?
hi chenjia,
in my test.
1.use the same inductor, if use a resistor parallel connection with inductor, the output is stable(reduce the resistor). if not, the output is unsatble.
2. load is resistor, the value of resistor did not affect the output current, it is always stable.
hi everyone,
in my designing , the phase margin is about 60 degree. in our test, add a resistor as load, the ouput current is stable, add a inductor (voil coli motor) as a load, the output current is oscillation.
could you give me some suggestions about this circuit?
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