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Does anybody know a circuit architecture for a programmable frequency divider that can divide from 1 to 62 USING PULSE SWALLOW LOGIC? I need it to divide by 1, 2, 3, 4, 5 upto 62 depending on its control inputs......
when we analysed the behaviour of type2 systems in 'pll design assistant' tool written by michael perrott, we observed an extra pole zero pair in the pz plot..can anyone post the reason behind this.
What are the methods to reduce lock in time of PLL? Will the logic with coarse and fine PFD reduce the lock in time and improve the performance??
Can you suggest a logic to switch between coarse and fine PFD??
sir
We are using D flipflop logic for implementing phase detector in PLL.But even after reseting, the outputs(up & down signals) of the phase detector are oscillating.Can you please suggest some solutions to this.
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