Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi Brilliant People,
I am currently studying this new type of transistor technology called the FDSOI. I am confused or know little about how these secondary gate are achieved/work and how is it related to its bulk bias potential?
And how is Vt is adjusted by placing P or N well beneath the...
Hi,
Thanks for the reply. By the way, can you expound the first paragraph more? Is that stray capacitance is equivalent to capacitance of the power rails when you use parasitic extraction tools?
Thanks,
meeyaw
Hi,
I have question that currently tricks me. Here is diagram for the reference for my questions
gpwr is a power gated supply when PWRPMOS is enabled.
1.In my current SPICE run, the bounce on the gnd is higher that drop in the pwr rail. Is that possible?
2. Based on the diagram, i expect...
Hi all,
I am currently studying current measurements of circuits when I suddenly got stalled by this block that I am currently studying. Diagrams below are provided below:
Block:
Behavior:
The block intends to be a STOP_CLOCK cell. By the name itself, it will stop CLK_IN whenever STOP...
Hi edaboard masters!
First of all, I don't know where to post this specific question but please free to move it to an appropriate thread.
And now for the question: does anyone here have done crosstalk analysis using SPF/SPEF? I just want to know how does the method been carried on.
Right now...
Hi,
The meanders are intended to add delay on the given path in the layout. The two devices are buffer circuits, parasitic RC being extracted. The line and vcc and vss shield are on the same metal layer, say M4, and the meander clock line is about 400um long (including the bends), 0.3um wide...
@andre_tempron
Does less breaks in paths means less susceptible to coupling/reflection?
Other help needed: How can I translate it to a circuit model to have a simulation for both cases?
Thank you very much.
Hi edaboard people,
Please help me about this problem shown in the attachment image.
I have two possible routes for a clock line from device A to device B. As you can see, CASE A has more loop than case B. Both cases are shielded by vcc-vss pair.
The question is, which one is more prone to...
Hi rahul,
Thanks for the very informative answer as well as easy example. Two questions though:
(1) at when STA a back-end engineering or a front-end engineering? This is where my confusion comes in
(2) is Synthesis is a front-end? (note: i am not very well familiar with this Synthesis, since...
Hello experts in edaboard,
Though I am quite familiar on how semiconductor design companies work, i still puzzled with words back-end engineering and front-end engineering. Can you help me understanding these terms? If possible, can you give examples of VLSI design process that are back-end or...
To clarify the query above, when I say adaptive, it means that the design is stable across PVT, or its slew rate is adjustable to the number of loads it drives or the drive current - some sort of like that.
I have asked this because I want to see other ways of designing clock buffers for...
Hi all,
Is anyone here started/already designing clock trees/mesh using adaptive CMOS buffers? Then, what are the things to consider in doing those things.
I've asked this as I was trying to do a self-research on CMOS buffer implementations.
Thank you very much for the answers.
The diamond markers is only an indicator of regions (MOS finger) of high current density. The tool doesn't account for non-uniformity of the current flow in that finger.
The color scheme of the tool is based from the current density criteria I have set based from the tool manual for usage...
I know that power is different from electromigration.
Sorry for somewhat misleading you.
The one that I have been analyzing is electromigration on the power rails caused by the currents flowing into the metal tracks when the CMOS is in switching from logic 0 to 1 (hence the reason i...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
