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actually I am trying convert verilog code to vhdl...
and the module is instantiated by other modules..
while simulating verilog code its not showing any simulation error and the counter is going upto 100.
but when i converted the same module into vhdl then when the count value reach 87...
function my_integer (constant A:unsigned (4 downto 0)) return integer is
variable B : integer range 0 to 23;
begin
B := to_integer(A);
return B;
end;
but again I am getting the same error while simulating... I want a memory depth of 24 only.. how would i ?
inputs and signals:
sig_word : in unsigned( 23 downto 0 );
signal sig_data : std_logic;
signal sig_counter : unsigned( 4 downto 0 );
sig_data <= sig_word(to_integer(sig_counter) );
Iam getting the warning in the above line of the code.
since sig_word expects a range upto 23. but...
i have no idea why i am getting latch infer warnings in this code below
and i made sure that all cases covered including default case.
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
entity freqdomaintrainingseqmem is
port (...
While simulating my vhdl code in modelsim.
I am getting some warning like
-----------------------------------
# ** Warning: NUMERIC_STD."/=": metavalue detected, returning TRUE
# Time: 0 ps Iteration: 0 Instance: /---/--/--/--
-------------------------------------
And I am getting the...
hi..
while simulating a vhdl entity using verilog testbench using questa simulator i got the following error
----------------------------------------------------------------------
# ** Error: (vsim-3043) /home/lma/lma-verilog/ca/questa/states_chain_test.v(728): Unresolved reference to...
systolic implementation available on the net try using the search terms "systolic implementation of montgomery modular multiplier"
or in opencores.org as our friend "tricky...," said
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