how to make xilinx ise libraries visible in questa simulator library???

[me0414013]

hi..
while simulating a vhdl entity using verilog testbench using questa simulator i got the following error
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# ** Error: (vsim-3043) /home/lma/lma-verilog/ca/questa/states_chain_test.v(728): Unresolved reference to 'cap_ac0_aifs_r' in uu_acmac_cap_tb.U_CAP.cap_ac0_aifs_r.
# Region: /uu_acmac_cap_tb/test
# ** Error: (vsim-3043) /home/lma/lma-verilog/ca/questa/states_chain_test.v(728): Unresolved reference to 'cap_ac0_backoff_r' in uu_acmac_cap_tb.U_CAP.cap_ac0_backoff_r.
# Region: /uu_acmac_cap_tb/test
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on searching on the net i found that we have to make the corresponding libraries visible to the simulator and we have compile the coresponding libraries.. can u please help me in this regard???
thanks and regards.

 

[mrflibble]

There's a few older posts on this subject. Search the forum on "compxlib". Or google on "compxlib questasim" or compxlib modelsim" for more info.