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Recent content by McSim

  1. M

    Self-heating simulation

    Thanks, Keith. Yes, sure, we used this manual, but there is only a picture with thermal R and C (I will post it here a little bit later), but it's unclear for me how a simulator solve the equations for SHE. Let's consider the simple example: 1) Ids is calculated. 2) P=Ids*Vds. 3) A simulator...
  2. M

    Self-heating simulation

    Dear colleagues! I deal with SPICE models for SOI MOSFETs. Self-heating effect is one of the most important problems for the designer because it's difficult to obtain the values of cth0 and rth0 parameters. My objective is to study or create the methodology for the extraction procedure for...
  3. M

    Trouble with veriloga in Spectre 6.x simulator

    All model and instance parameters are described in module as instance parameters (e.g., parameter real W=...; ... parameter real U0=...; ) In Spectre 5.1.41 there's no option to mark out "instance parameters" (like "(* instance_parameter_list ’{parameterList} *)" in Spectre 6.2). Therefore all...
  4. M

    Trouble with veriloga in Spectre 6.x simulator

    Hi all! I have a problem with Verilog-A modeling in Spectre 6.x. I use BSIM3 model implemented in Verilog-A by Geoffrey Coram (the file was available at Silvaco and then - at Simucad site some time ago). See attached file. I have successfully used it with Spectre 5.1.41. My "standard" task is...
  5. M

    MOS transistors parameters mismatch modeling

    Mismatch modeling Hi! I want to simulate MOS transistors parameters mismatch (for example, Vth0 parameter of BSIM3v3 model) using Monte Carlo analysis with Spectre simulator. I've created a "sample" model file with "statistics" block. Process parameters deviation was simulated successfully...
  6. M

    Cadence Layout (help)

    Layout pins names must be identical with schematic pin names. Otherwise, your LVS will report the error message (but you will still be able to run RCX procedure). As I understand your problem, your layout and schematic pins names don't match. P.S. By the way, creating config is not the only way...
  7. M

    How to measure/simulate sink/source current of I/O cell?

    Hello! I'm not sure that I've chosen the proper forum section for this topic, sorry if I'm mistaken. Please explain me what is the "source/sink output" current (how to measure it and how to simulate it using SPICE) of I/O cell? As far as I understand it is just a DC output current via resistor...

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