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Trouble with veriloga in Spectre 6.x simulator

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Newbie level 4
Nov 15, 2007
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Hi all!

I have a problem with Verilog-A modeling in Spectre 6.x.

I use BSIM3 model implemented in Verilog-A by Geoffrey Coram (the file was available at Silvaco and then - at Simucad site some time ago). See attached file. I have successfully used it with Spectre 5.1.41.

My "standard" task is to simulate MOSFET DC characteristics. Transistor is taken from PDK. In model file there is a subckt which uses the instance described as Verilog-A module (using "ahdl_include"). All SPICE parameters are described as instance parameters (instance inside subcircuit):
inline subckt nmos_tn (d g s b)
parameters w=1E-7 l=1E-7 PAR=1 as=0 ad=0 ps=0 pd=0 nrd=0 nrs=0
nmos_tn (d g s b) bsim3mos W=w L=l AD=ad AS=as PD=pd PS=ps ...
+ TYPE=1
+ U0=0.035597185
ends nmos_tn

, where "bsim3mos" is verilog-A module.

But when I try to simulate this with Spectre 6.0 or even with Spectre 6.2 some Verilog-A module parameters are not recognized as instance parameters by simulator (and some parameters, e.g. W, L, TYPE and TOX are still recognized, but U0 isn't). Warning message is generated:

"U0 is not a valid parameter for an instance bsim3mos. Ignored"

And then characteristics with default values (defined in Verilog-A module) of parameters are simulated.

Could you help me to solve this problem or just give an advice how should I search the possible reasons?

P.S. By the way, does anybody know why the files with Verilog-A MOSFET models are not available now?

Why are you passing all those parameters in on the element
card? Those are model params, and they belong inside
(or pulled in by some means, like from the variables
list or an include-file) the "model" file (veriloga).

All model and instance parameters are described in module as instance parameters (e.g.,
parameter real W=...;
parameter real U0=...;
In Spectre 5.1.41 there's no option to mark out "instance parameters" (like "(* instance_parameter_list ’{parameterList} *)" in Spectre 6.2). Therefore all parameters are instance parameters by default.

Those are model params, and they belong inside
(or pulled in by some means, like from the variables
list or an include-file) the "model" file (veriloga).
Do you mean passing all model parameters as construction like this:

inline subckt nmos_tn (d g s b)

nmos_tn (d g s b) mos_model w=w l=l ad=ad as=as pd=pd ps=ps ... 

model mos_model bsim3mos 
+ TYPE=-1
+ LMIN=1.8E-007             LMAX=3.5E-007             WMIN=2.2E-007
+ WMAX=6E-007               VERSION=3.3               MOBMOD=1


I've already tried it. No effect. :(

Added after 1 hours 40 minutes:

I've solved my problem... The reason was just one string in simulator options:

simulator lang=spectre insensitive=yes

The correct variant is following:
simulator lang=spectre

There was intrinsic conflict with parameters in upper register (which were instance parameters) and lower register (local variables).

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