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Hi. Yes I know. I will also try that but 4 back to back switch may fail to bring it down properly given the voltage headroom. Will check anyways.
Although it is 12 bits, I have a max INL of 2LSB spec, funny huh, but I hope it will make things much easier.
The amplifier's gain is on the good...
Hello again. It is ok, I could have explained better I suppose.
I'd like to thank you very much for the suggestion. The total switch size is now like half. (it used to have the following scheme: 1+1+2+4+8+16+32+64+128+15*256 unit cells, now 2+2+1+2+4+8+16+32+64, + 15*128 cells). Since this...
Hi, I was in a hurry, the drawing is incorrect. Normally it is in non-inverting configuration.
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Hello again. Could you take a look at the drawing I attached now? Can you explain to me why this would be ruining every branch? When you take a look at the impedances from an...
Hello. I did not really understand your concept but unfortunately I cannot afford to create such a unit cell as I already laid out the resistor core. Time is of the essence too. I am all ears if you have any other insight about this. Thanks a lot.
Hello, attached is a representative drawing I just made, excuse me for the image but am away from my terminal and did not want to lose time.
Let me try and clarify things further. Yes you are right, this is based on a Vref. And the input resistance is code dependent. What I tried to do here via...
Hi all,
I designed a 12bit DAC based on R-2R topology in a 0.18um CMOS tech. It is 8+4bit segmented. The sizes of the switches are increased in a binary weighted manner as the current drawn from each consecutive higher significant bit is going to be double. So, the switch of the LSB is 1 unit...
Hello again, I tried what you suggested, and it indeed corrects the behaviour as can be seen from the graphs. So, huge input capacitance and combination of Rout is causing this? If so, why do we still do not see this in the closed loop, when I also add a dummy replica of the circuit to the...
Hello again, here are the schematics for the circuit itself, and the higher hierarchy tests views. Rout you see at the output is 10k ohms (output is low impedance thanks to the source follower anyway).
Thank you for the reply.
It's a conventional diff pair followed by a source follower (actually it's a flipped voltage follower but I do not think it has anything to do with this issue). Right at the output of the diff pair (or at the input if the source follower), there s an intentional...
Re: bizzare buffer AC response
Here are the open loop and closed loop AC simulation results.
Can we say that the PM seen at the open loop is just an illusion?
Hello all,
In one of my schematic level designs, for an analog amplifier, PM is supposedly 92 degrees. But when I used it in a buffer configuration, i noticed that for a square pulse, there were ringing during the slewing! I never experienced something like that. It could ring during settling...
Hello all,
I have designed a Class AB amplifier, schematic level simulations suggested a gain of 93dB, yet after parasitic RC extraction with Quantus PVS, post-layout simulations suggest 10dB less gain. Do you have any insight what might be the reason? There is no gain drop if the extraction is...
Hello,
I am indeed using Cadence. I have put the iprobe instance in series with the cap but Where should I examine the gain and phase? I mean which two points should those be to select when choosing gain&phase? I am a little confused. If it was an opamp, i would have looked to the gain and...
Hello, I am designing a slew-rate controlled digital output driver. The simplified output stage is attached. The feedback is done via the capacitor at the picture from output to a switching nodes. You can see the two switch transistors in rectangular.
Here, I am also adding series resistors to...
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