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Thanks for responding, I really appreciate it.
Idle curiosity, true. I tend to overthink things. Regarding the app notes of vendors: my interest was chip design related, not so much application. So, for example the non-inverting opamp/buffer which I mentioned: I guess topology choice is not...
Good morning,
Recently I've been looking into Opamp/OTA design. While there are tons of readings available, most are quite theoretical. But I’m kind of lost which architecture is best for certain applications. Does anybody know some good literature, which not only explains the OTA/Opamp, but...
Hello Dick,
thanks for the suggestion. Tried it a couple of times, but so far I get the same outcome (or I have an incorrect setup). Perhaps important to mention, it’s a SOI process. Other poly-like resistors show similar behavior, however high-res N+ poly does not.
Hi all,
Small question regarding the ‘R’ curve of polysilicon silicide resistor when sweeping the input voltage from negative to positive. As a result, I get a parabolic curve, negative or positive depending on N+ or P+. After a some searching this apparently what I can expect: there is a (V/L)...
Hi all,
While simulating the output current of a 1uA current mirror I noticed a strange behavior. It’s a straight forward mirror: output is NMOS + cascode NMOS (biased at 950mV), 65nm PDK and 3V devices. Ideal supply and ground. While sweeping the output voltage I noticed an increase in current...
Sure. Below is (part) of the circuit:
...note: it's not complete, but only the interesting part is displayed. The bulk of Mp3 is also connected to a max voltage selector. If the drain of Mp3 is low, the gate must be VDD. If the drain is higher then VDD, then the gate must be equal to the...
Hey all,
I have a simple max voltage selector (2x 3V3 PMOS, alternative design is 4x stacked PMOS). Inputs are VDD (fixed voltage reference) and VSEL (more or less digital waveform). The output (which is always the highest voltage) goes to the gate of a fairly big PMOS. In principle this works...
Hi all,
quick folded cascode question. Looking at some lectures slides, I stumbled upon the following slide/requirement:
It's the first comment. What would be the reason that I4 & I5 has to be 1.2 - 1.5 times I3? In other designs I noticed that they are mostly equal, I4=I5=I3. Also does the...
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