Analog design: max voltage selector

[maxporter]

Hey all,

I have a simple max voltage selector (2x 3V3 PMOS, alternative design is 4x stacked PMOS). Inputs are VDD (fixed voltage reference) and VSEL (more or less digital waveform). The output (which is always the highest voltage) goes to the gate of a fairly big PMOS. In principle this works fine, unless VSEL is changing rapidly and the high state is equal to VDD. When VSEL is ramping up from 0 -> VDD, eventually all PMOS goes off, the gate connection becomes high ohmic, causing a large initial spike (>4V5) which degrades slowly back to 3V3. Since this potentially could damage the gate, is there a way to avoid this? Or perhaps provide some kind of discharge path (preferably without wasting static current).

Thnx in advance.

 

[KlausST]

Hi,

your description is not clear to me.

Can you draw your circuit? With voltage and timing informations.

Klaus

 

[maxporter]

Sure. Below is (part) of the circuit:


...note: it's not complete, but only the interesting part is displayed. The bulk of Mp3 is also connected to a max voltage selector. If the drain of Mp3 is low, the gate must be VDD. If the drain is higher then VDD, then the gate must be equal to the drain. The waveforms when VSEL=VDD:

Blue is gate, red is drain Mp3.

 

[erikl]

Can you clamp max-sel to VSEL by a diode? This should at least limit the high tip of the spike.

 

[maxporter]

...that's worth a try, thanks for the idea.