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Recent content by Maulik Suthar

  1. M

    SystemVerilog Model Design

    Hello all, I am currently working on a model design for a memory, that memory has 32 independent ports and also has control signals and other stuff. I want to implement a class based model in which i can write and read into a memory from 32 channels which run parallel to each other but the...
  2. M

    AHB 22 APB Bridge Verilog design

    Hello, I am studying AHB and want to implement a simple AHB2APB bridge without split/retry, I have 2 modules inside my bridge 1. AHB Slave + Address decoder and 2. the state machine for APB. i have no clue how to start with the ahb slave and what functionality to implement. it is a single master...
  3. M

    UVM: explain do_copy method in detail

    still i am not clear with the do_copy function, i will be glad if u elaborate a little thank u
  4. M

    UVM: explain do_copy method in detail

    hello, i want to know how exactly a do_copy method works? what is the need of $cast(rhs_, rhs)? and also why to call the super.do_copy(rhs)?? function void write_xtn::do_copy (uvm_object rhs); // handle for overriding the variable write_xtn rhs_; if(!$cast(rhs_,rhs)) begin...

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