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AHB 22 APB Bridge Verilog design

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Maulik Suthar

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Hello,
I am studying AHB and want to implement a simple AHB2APB bridge without split/retry, I have 2 modules inside my bridge 1. AHB Slave + Address decoder and 2. the state machine for APB. i have no clue how to start with the ahb slave and what functionality to implement. it is a single master bridge so i wont be using Hselx signal, no hproct, have 2 transfer type NONSEQ nd SEQ, and supports all burst and wrapping mode. plz guide me how to start the design first the AHB slave and Decoder part.
 

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