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Re: Diffusion butting
Butting is not recommended in some cases (analog designs), related to the noise injected into the substrate.
If the bulk diffusion is close to the source of a transistor carrying a large current, acting as a switch, for example, the noise injected in the substrate is...
You have a loop gain that is equal to the sum of all gains in it. So, at the critical phase you need an overall loop gain smaller than 1 (0 dB). If you increase the output gm, the gain introduced by that transistor, requires a smaller gain at the output of the opamp (usually). This means more...
"More output gm, more far poles from origin" True, but the overall loop gain increases and compensation becomes more difficult. So I recommend that the gm at the output to be as low as possible for WC conditions.
kobeghost : Could it be that at the output of the opamp in your schematic, you have a PMOS driving the R/PNP loop, and the compensation capacitor(at the output of the opamp) is to VSS? If it is, than do yourself a favor and put it to VCC, so that PMOS to have constant Vgs.
Another way to...
If you are worried about closed loop stability, than I belive the resistive load at the output is not too important, but the capacitive load is important because the pole of the output transistor, moves towards the origin, disturbing the phase at which the loop has unity gain, resulting in an...
If the models from the fab don't have MC data, then you have to introduce it manually. In your netlist/sch, you parametrize the transistors you choose, set the distribution type, and after that you run MC. I work with Hspice, didn't use Cadence for a long time now, and can't tell exactly, except...
Re: Anti Parallel Diodes
"But one doubt, why not the same implementaion for VDD rails as well ?"
Because the NWELLs are (usually) tied to VDD, and their noise isn't propagating in the whole chip, as is the case of the GND-tied p-substrate, which is one for the whole chip. I think... Thank...
cmos power equation
Of course the transition time is affecting the switching power dissipation. The longer transition time, the longer time the inverter has both transistors opened, permittting the current to flow from the power supply
to ground.
If the inverter doesn't drive a long line...
tlu+
Astro/Milkyway I belive that are P&R tools, and Calibre and Hercules are used for LVS needed for the transistor level parasitic extraction. It means that StarRCXT is able to read those tools' output databases...
calibre query star rc
"Is there any way to extract parasitics with Star-RCXT, but to have all the devices extracted and the RC data only on the nets of interest? "
To be more clear: I asked if it is possible to extract PARASITIC INFORMATION only on the specified nets, but to have all the...
star-rcxt lvs option
Hello,
I have the following problem: I want to do a parasitic extraction with Star-RCXT, but to keep the RC data, only on a list of nets of interest. Made the list with the nets, ran the extraction, and after a while, realised that the output netlist contains devices and...
Hi,
Can someone tell me if there is any way to generate hierarchicaly extracted netlists with Star-RCXT, in any of the SPF or NETNAME formats? Can this be done with other extraction tools?
Thanks!
Re: GDSII files
what tool are you using? In Cadence, for example you have export stream for exporting gdsII files and you can export anywhere you want. I'm not sure if the layout database (the file containing the layout information ) is a true gdsII type file.
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