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while building a clock tree
There are three important parameters for such nets:
***Transition time:- This is the time it takes to change the logic level of a node (e.g. 0 ! 1).
***Insertion delay:- The time required for the signal to travel from the driver to the end-points.
***Skew :-...
Reports global as well as specific instance power, clock network power, clock domain power,
and net switching power. It also reports the power for power domains and specific power nets.
Units are reported in milliwatts...u can use certain commands regarding this along with
report_power..
(EX)...
hi
I have to place bond pads on the IOs.. I have done the following changes but still I couldnt get bond pads placed...Is there any other changes I have to do
I have changed in LEF
1.I have included at the top of the LEF file.
PROPERTYDEFINITIONS
PIN bondPadOuter STRING ;
PIN...
hi...
I think u can synthesize using two different sdc's ...but the thing is clock given for two blocks should not be same ... I have tried with two different sdc's for single block which has two different functionalities..
hi...
In SOC Encounter end cap definition is
End-cap cells are preplaced physical-only cells that are required to meet certain design rules.
They are placed at the ends of the site rows, and are used in some technologies for power.distribution. End-cap cells are placed in a preplaced status...
Hi...
steps to remove Setup violations:
=> upsizing the driver (ecochangecell -inst inst name -upsize)
=> Downsizing the receiver
=> buffer long wire (ecoAddRepeater -term inst name -cell cell name)...
Hi,
For floorplaning tried to learn how to decide core width and height based on placement density...... learn power planning commands,and how to align pin location
For timing optimisation u have to come across these terms setup, hold, skew violations, slew...
hi
I am doing top level using encounter..My Macro block has power net connections as VDD VSS and power connections from pad is VDDD VSSS how to connect these two different power nets...
hi
We can add any kind of buffers in CTS neither small nor large drive strength buffers..But in case of small drive strength buffers the delay will be large..We do CTS in order to match the data and clock path only so If delay is high it seems difficult..
In case of large drive...
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