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Hi,
In my design we have a clock mux whose select line is driven by positive edge trigerred flip-flop. I know that its difficult to meet hold check in such scenario because hold check will be done from launch edge to next half cycle edge.
In that case if I do an MCP of 2 on setup and MCP 1 on...
Thank you for the responses.
I understand that Reset won't work without 0-> transition. No concern there.
My understanding is we need reset only because we dont want the chip to start with unknowns.
Lets say I am fine with chip starting with unknowns and confident it will get to a steady...
I understand Reset won't work with 0->1 transition.
What if I dont want to reset and ok with design starting with unkonwns. I am sure eventually it will settle to known state after some cycles. If I held Reset high it should come out of reset right?
Hi,
I have a question regarding resets to flipflops.
I understand that if you reset flipflop will start in known state.
For an active low reset flip flip what happens when I give a static 1 to reset? Will it start with Q<=d or will it be an indefinite 'x'?
Also in hardware what will happen...
Hi,
What do you mean depend on the EDA.
Isn't capture, shift and update general terms used in scan?
Even in IEEE TAP machine there are states for capture, shift and update.
Please advise!
Hi,
Can anyone explain in detail what does shift, capture and update mean in scan?
I know all the flops in the design are made scannable and form a chain. Now to test the design, there is scan-in, capture and scan-out.
I can relate shift and capture here but where does update happen and what...
systemc half_adder
Hi,
I am learning systemc and in the process wrote a test bench for half adder . when I tried to simulate it in modelsim it is giving the following error
# Model Technology ModelSim SE sccom 6.3 compiler 2007.05 May 4 2007
#
# ha_tb.cpp: In constructor...
function of flip flop delay
I dont have a reference but i can explain this way...
In a scan chain if one the flip-flop has hold time violaion then the output will appear one clock in advance. This is because the defected flip-flop cannot hold the value and acts as a buffer. This is how...
Re: Formal Verification
FV does equivalence checking between two designs. If a design is functionally verified then any further modifications to that design is formally verified with original design. This avoids multiple functional verification.
FV is generally done after DFT, BIST insertion...
flip flop setup time
Can someone tell me how a flipflop with setup time violation function? a flop with hold time violation will act as a simple buffer. In the same way how it acts with setup time violation?
Please let me know
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