Reset to a chip? does it have to be a pulse

[mailsrikanth007]

Hi,

I have a question regarding resets to flipflops.

I understand that if you reset flipflop will start in known state.

For an active low reset flip flip what happens when I give a static 1 to reset? Will it start with Q<=d or will it be an indefinite 'x'?

Also in hardware what will happen?

Basically Im trying to understand does reset always require a pulse? or a chip can directly start out of reset.

Please advise!

 

[FvM]

Reset must be
1. applied (nRes = 0)
2. released (nRes = 1)

Means reset can't work without at least a 0->1 level transition.

 

[KlausST]

Hi,

For ready to buy devices I assume "reset" to be an asnchronous and level sensitive signal.
For detailed informations consult the datasheet.

For XILINX libraries: (like counters)
* "reset" signals are synchronous signals, they react on the "clock" edge
* "clear" signal are asynchronous signals, they react on "clear" edge

Klaus

 

[ThisIsNotSam]

Hi,

I have a question regarding resets to flipflops.

I understand that if you reset flipflop will start in known state.

For an active low reset flip flip what happens when I give a static 1 to reset? Will it start with Q<=d or will it be an indefinite 'x'?

Also in hardware what will happen?

Basically Im trying to understand does reset always require a pulse? or a chip can directly start out of reset.

Please advise!

Weird questions bundled up. First thing to realise: there are many types of flip flops. Some reset to 0, some set to 1, some don't reset, some reset synchronously, some asynchronously.
For the first question, the answer is x.
In hardware you have paths fighting, behavior is not deterministic.
Some designs don't need resets if eventually they are able to achieve a stable state in their FSMs and wait for real inputs thereafter. That is not the generic case, however.

 

[mailsrikanth007]

Reset must be
1. applied (nRes = 0)
2. released (nRes = 1)

Means reset can't work without at least a 0->1 level transition.

I understand Reset won't work with 0->1 transition.
What if I dont want to reset and ok with design starting with unkonwns. I am sure eventually it will settle to known state after some cycles. If I held Reset high it should come out of reset right?

 

[mailsrikanth007]

Thank you for the responses.

I understand that Reset won't work without 0-> transition. No concern there.

My understanding is we need reset only because we dont want the chip to start with unknowns.

Lets say I am fine with chip starting with unknowns and confident it will get to a steady state after lots of cycles. Why can't I just held Reset high and expect normal functionality?

Below is the code for D flip flop

always @ ( posedge clk or negedge reset)
if (~reset) begin
q <= 1'b0;
end else begin
q <= data;
end

So if Reset is always high q = data. I know data will be x to start with but it should get to a steady state after some cycles.

Am I missing anything?

 

[dave_59]

The problem is when "data" is the output of another flip-flop, who output is also unknown. Or data could be some function of a known input, xor'd with q. You have no knowledge of what that steady state may be.

Another issue - your system might get into a state that it never would have gotten into. For example, you might have a counter that was supposed to reset itself when reaching a certain value. The counter could come up in a state you never expected.

 

[ThisIsNotSam]

Thank you for the responses.

I understand that Reset won't work without 0-> transition. No concern there.

My understanding is we need reset only because we dont want the chip to start with unknowns.

Lets say I am fine with chip starting with unknowns and confident it will get to a steady state after lots of cycles. Why can't I just held Reset high and expect normal functionality?

Below is the code for D flip flop

always @ ( posedge clk or negedge reset)
if (~reset) begin
q <= 1'b0;
end else begin
q <= data;
end

So if Reset is always high q = data. I know data will be x to start with but it should get to a steady state after some cycles.

Am I missing anything?

Well, yes. You are missing the fact that no large size design is built like this. it might be fine to have a few flops without reset here and there to save area, but not a whole chip. Just put a damn reset and be done with it.

 

[jt_eaton]

You can design without a reset and certain blocks like clock dividers that must function during reset do exactly that. But it only works for small blocks otherwise the verification is impossible and you still need another reset for simulation and test.


John Eaton

 

[slutarius]

Thank you for the responses.

I understand that Reset won't work without 0-> transition. No concern there.

My understanding is we need reset only because we dont want the chip to start with unknowns.

Lets say I am fine with chip starting with unknowns and confident it will get to a steady state after lots of cycles. Why can't I just held Reset high and expect normal functionality?

Below is the code for D flip flop

always @ ( posedge clk or negedge reset)
if (~reset) begin
q <= 1'b0;
end else begin
q <= data;
end

So if Reset is always high q = data. I know data will be x to start with but it should get to a steady state after some cycles.

Am I missing anything?

No one can say that "data" will be steady after some cycles ?
What is "some" here ?
If you have a loop logic from later stages FlipFlop back to your data logic,
how can you know since you q always get X ( unknown ) value.

Anyway, reset operation makes thing be clear and odered.
Without reset, there is just a mess.
Some can due with the mess himself, lot of us can not. So does the logic design.