Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I understand that. But in all of above solution, does the manufacture has to program the SN into the eeprom/OPT? imagine, if there are millions of chips taped out, they have to power up each chip, and program the OPT?
I am wondering if the fab has a way to etch different number into each chip...
Hi :
Assume I am designing an IC that will be in mass production, each chip will have a unique 32 bits ID. Apparently that has to be done by manuafacture, how will this be considered in RTL design phase? and how the manufacture will do it?
I only got experience on modeling an ROM, using...
Hi:
I am a beginner on VerilogHDL, what does the following statement do?
reg sum_out_shift[25:0];
reg sum_out_sat[7:0];
sum_out_shift <= {{18{sum_out_sat[7]}}, sum_out_sat};
Sign extending the sum_out_sat? Why "<=" sign was used , not the "=" sign?
Thanks
chris
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.