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dear all:
i am designing a current reference(PTAT),but i dont know how to choose the resistor .there are so many kinds of resistor supported by the foundry,polyres,Pbaseres,etc.a few of them are low precise,but many of them have precision of 10%,i am confused about choosing,is there any advice??
hello,everyone
i am considering the physical meaning of half plane zero,i learned that there will be a zero produced when there are two signal paths from input to output.
but there is also a zero at the output of a LDO which is produced by the ESR and output capacitor,i dont know how this...
thank you ,dick_freebird
you helped me a lot.about my last question,i forgot to told you that the time averaged current is less than 0.1mA(so it can be ingored).
and i have another question:where can i find the hard set of electromigration groundrules you talked about? i read all the documents...
thank you, dick_freebird
according what you said, the 17um-width thick metal2(maximum current density is 3.5mA/um) can meet the need of 600mA current pulse(sub-1us),am i right?
help me with the transient current problem
hello everyone
i am new on power management IC design,and i am confronted with a problem:according to the process application note,the maximum current density of metal2 is 3.5mA/um,how wide should i draw for metal2 if transient current which last...
hello,dear all
i got a error message when i use calibre to run PEX,the error message is :
ERROR:Unable to open pdb:"svdb/amplifier.pdb
how can i solve this problem?can anyone help me please?
hello,WimRFP
for "the operating point", i mean the DC bias voltage. i am not good at english,sorry to make you confused.as you said "This AC voltage is centered around the DC bias voltage in B",i found the AC voltage is below the DC bias voltage in B,maybe that is because i didnot manage to keep...
thanks,WimRFP,
sorry for replying so late,my network is not always available.
for the "operating point",i mean the resulted voltage by applying a dc power on the gate.
you said"Vb will be determined by the division between C1 and the other mosfet capacitance ",could you explain it concretely?thx!
wimRFP,thanks for your replying.
quote:Vb will be determined by the capacitive division between C1 and the other mosfet capacitances.
but the higher peak voltage at node B is always at its operating point as long as the frequency of V1 is high enough,when i change the capacitance of C1.how do...
dear everyone
i want to know about zeros of circuit,so i build a circuit shown below:the capacitance of C1 is about 20pF;V1 is a sin signal,its offset voltage is 1V,and its amplitude voltage is 10mV.when the frequency of V1 is higher than about 1MHZ,the voltage at node B is a sin wave,whose...
thank you,leo_o2,it is nice to meet a compatriot on an foreign forum
i already know what you said,i wonder whether this topology is popular,since i meet this circuit for the first time.
and i have another question to ask you:
how high should i set for the opamp if i use an opamp to force the two...
hi guys
i am analyzing this bandgap circuit,i want to know whether this bandgap topology is popular,and what is the andvantage and disadvantage of this circuit.
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