Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by lins13

  1. L

    Control Signal Logic Levels

    Thanks for the idea but I am going to use a comparator. I have very little drive current available and this lets me change the voltage levels and invert in one device.
  2. L

    Control Signal Logic Levels

    if I do this, will it not make the high equal to 6.6V in addition as it is one track for both signals? That would be a problem
  3. L

    Control Signal Logic Levels

    Hi Guys, I have a signal which I must use as a control signal for a DAC. However the device the control signal comes from holds the signal at -3.3V for a low and +3.3V for a high. This cannot be changed. I need the signal to sit at 3.3V high normally and pulse to 0v for a low...
  4. L

    Phase Locked Loop, Loop Filter

    Thanks for the response So just to be clear and confirm this: wn is the same frequency as the loop bandwidth, i.e. the point were the loop gain is 1. The 3dB bandwidth of the filter chosen as the loop filter can then be calculated from wn through wn = sqrt (KoKd/t1+t2) if the filter is passive?
  5. L

    Phase Locked Loop, Loop Filter

    Hi guys, I am a student currently working on a project to design a phase locked loop and I have a problem with designing the loop filter, which is a passive lag like in most textbooks. Basicly I am designing and building a PLL for a pretty specific scenario where noise performance...

Part and Inventory Search

Back
Top