lins13
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Hi guys,
I am a student currently working on a project to design a phase locked loop and I have a problem with designing the loop filter, which is a passive lag like in most textbooks. Basicly I am designing and building a PLL for a pretty specific scenario where noise performance is the upmost concern. My question is this:
I have a chosen loop BW of my PLL, constrianed by where my XOSC (input reference) phase noise and VCO phase noise cross so to have the best phase noise at my PLL output. I also have the K values of my VCO and PD. Now what I am unsure of is wether this loop bandwidth frequency is equal to wn (dosent make sense to me from its definition) or whether it is the frequency I should make the 3db point of my loop filter. I can't find this anywhere and need to solve it to use the design equations from Roland E Best's PLL textbook
Would really appreciate if someone could clear this up for me
Thanks
Lindsay
I am a student currently working on a project to design a phase locked loop and I have a problem with designing the loop filter, which is a passive lag like in most textbooks. Basicly I am designing and building a PLL for a pretty specific scenario where noise performance is the upmost concern. My question is this:
I have a chosen loop BW of my PLL, constrianed by where my XOSC (input reference) phase noise and VCO phase noise cross so to have the best phase noise at my PLL output. I also have the K values of my VCO and PD. Now what I am unsure of is wether this loop bandwidth frequency is equal to wn (dosent make sense to me from its definition) or whether it is the frequency I should make the 3db point of my loop filter. I can't find this anywhere and need to solve it to use the design equations from Roland E Best's PLL textbook
Would really appreciate if someone could clear this up for me
Thanks
Lindsay