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I've corrected it. I've discovered that the standard cell core gate uses basicLib suplies, with those following expressions:
vcc_inherit [@vcc:%:vcc!]
vdd_inherit [@vdd:%:vdd!]
gnd_inherit [@gnd:%:gnd!]
vss_inherit [@vss:%:vss!]
So, the correct net to use with netSet was the supply name...
I'm designing a PGA with a small digital block to control gain selection within it. I used process standard digital cells to make the logic and it worked fine in schematics, but it caused problems with my layout because it doesn't share the same power nets. I used to just override those power...
Hello, fellow designers.
Currently, I'm dealing with the challenge of designing a ultra low highpass filter with the cut frequency below 1 Hz. That demands very large capacitors and resistors, and it's very hard to be make them inside ICs. The solution was to make pseudoresistors using MOS in...
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