vdd! net override using netSet property

[lhrodovalho]

I'm designing a PGA with a small digital block to control gain selection within it. I used process standard digital cells to make the logic and it worked fine in schematics, but it caused problems with my layout because it doesn't share the same power nets. I used to just override those power nets using netSet properties in my training, using XFAB process. Now I'm using AMS HIT-kit and it doesn't work anymore.

It seems that those standard cells don't have net expression and they are made using gnd! and vdd! symbols from analogLib. The XFAB process had the nets power_vdd and ground_gnd for those nets and it was easy to override them. When I looked at the spectre netlist of my block, it showed vdd_inh and gnd_inh in its pins, but I had no success trying to override them using netSet.

I've researched the following tutorial and also an old Cadence tutorial.

https://secure.engr.oregonstate.edu/wiki/ams/index.php/Cadence/InheritedConnections

 

[erikl]

... I had no success trying to override them using netSet.

Probably the corresponding AMS lib doesn't allow you to change the cell. So I'd suggest to copy this cell with a (preferably slightly) changed name to your own lib and make the necessary modifications in this new cell.

In your design you can selectively select all the cells with the old name and replace them all at once by those with the new name.

 

[lhrodovalho]

I've corrected it. I've discovered that the standard cell core gate uses basicLib suplies, with those following expressions:

vcc_inherit [@vcc:%:vcc!]
vdd_inherit [@vdd:%:vdd!]
gnd_inherit [@gnd:%:gnd!]
vss_inherit [@vss:%:vss!]

So, the correct net to use with netSet was the supply name without !

Note taken for ams HIT-kit