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in D-flip-flop method, div-by-2 circuit is built easily, that is the basic cll of a counter, but with cmos latch method, because it is level-sensitive, not edge-sensitive, so, div-by-2 circuit is difficult to build using only cmos latch(two inverter back-to-back, only half of a D-flip-flop)...
i have an idea, i want to build a counter with cmos latch(two inverter back-to-back connected), not with D flip--flop, may i?
but i got the bad results, it did not work.
can anyone give me some advice? can this be realizable?
i find another phenomenon, that is, the current ratio is related to vds of MOS pair, when vds of MOS pair is the same value, the current ratio is correct(1:4); with the increasing of vds difference of MOS pair(vds1-vds2), the current ratio becomes larger, from 1:4 to 1:40 or larger.
in my...
i have designed a current mirror with W/L=15u/20u m=1 to m=4, that is, a 4 times gain.
i use umc018 process. but my input current is very small, 0.5pA~2pA, then, i find that, when input is 0.5pA, the output is 20pA, when input is 2pA, the output is 26pA. it is not a 4 times amplification. it...
in umc 0.18um process, there is zero vth transistor(only NMOS).
1, Can PMOS zero vth transistor exist? why?
2, what is the normal use of zero vth transistor?
3, i build a current mirror with the zero vth NMOS transistor, but i have found that, the mirror ratio is wrong, i design it to be 1:10...
ok, thanks d123.
my question is that, in 0.18um process, vdd=1.8V, then, can VDS of NMOS tolerate 3.3V or more? and what is the maximum VDS of NMOS? is it 1.98V, 3.3V, or others? why?
for 0.18um process, vdd=1.8V, what is the maximum VDS for NMOS/PMOS?
for 0.35um process, vdd=3.3V, what is the maximum VDS for NMOS/PMOS?
what is the reason or principle of maximum VDS?
thanks.
thanks all.
i just want to know which technology or foundry can provide human-sensed coating or color filter for ambient light sensor,and at the same time, can provide native or Low-Vt MOS transistors. and 0.35um process is preferred here.
hi, KlausST
i know what you said, but i need to design an ALS IC (photodiode + current amplifier) to provide a large output current, suc as, 100Lux illumination will output 100uA current, the similar type is Avago APDS-9005. so, i need the above metioned technology, and i need more ideas, thanks.
hi, i want to design an ambient light sensor with analog output, that is photodiode+current amplifier, and the spectrum is human sensed, from 400nm to 700nm. peak=520nm, so i want to satisfy the following:
1, color filter or anti-reflection coating for 400nm-700nm spectrum, such as CIS process...
but it is the ral thing i observerd in my circuit test. so, it may be caused by the coupling between the signal generator connector and the input connecting wire (which connects input pin and the diode). if i put the signal generator connector away from the chip, then the antenna effect...
i have post my circuit in #15, about #10, i have explained for that, if i connect input to ground, then the circuit will saturate, then none signal will be recepted, and output is always high.
thanks.
thank you first. 200-300us is the duration of the output pulse, but it is a demodulated signal, so i don't know the interference frequency when un-demodulated. the 0.22MF capacitor is the power filter cap, even i add it to 10MF or 100MF, the spurious pulses are still the same, besides, what do...
no, it is not related to any communication system, but when i generate a 38khz modulated signal using a signal generator(a modulated current pulse to simulate the photo signal), even the connector of signal generator is not connected to the input pin of the receiver IC, the IC can still output...
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