what is the maximum VDS

[lhlblue]

for 0.18um process, vdd=1.8V, what is the maximum VDS for NMOS/PMOS?
for 0.35um process, vdd=3.3V, what is the maximum VDS for NMOS/PMOS?

what is the reason or principle of maximum VDS?

thanks.

 

[d123]

Hi, it might have something to do with the insulation capability of the device materials. I hope this attached document can help you and isn't a waste of your time; not sure but - for example - page 14 discusses VDS-SAT, you'll understand more than I can.

View attachment MOSFET Device Physics and Operation.pdf

 

[lhlblue]

ok, thanks d123.

my question is that, in 0.18um process, vdd=1.8V, then, can VDS of NMOS tolerate 3.3V or more? and what is the maximum VDS of NMOS? is it 1.98V, 3.3V, or others? why?

 

[erikl]

my question is that, in 0.18um process, vdd=1.8V, then, can VDS of NMOS tolerate 3.3V or more? and what is the maximum VDS of NMOS? is it 1.98V, 3.3V, or others? why?

This depends if this 0.18µm process has more than one gate oxide thickness option(s): with the usual tox ≈ 30Å , max. VDS is 2V (1.8V + 10% = 1.98V). For VDS=3.3V (or higher) you need one or more process option(s) with additional thicker gate oxide(s).

For 3.3V you need tox ≧ 70Å , for 5V: tox ≧ 200Å .

 

[dick_freebird]

There is no single meaning or rating. Every foundry develops
its technology for applicationa and end markets which have
different reliability and cost requirements. Vds ratings in the
design kit have mostly to do with long term reliability, but
this in turn depends on the application "use model" - time
at temperature, high temp or low temp having different
drift & wearout mechanisms; service factor; even the
simple expectation differences between (say) digital where
a 10% EOL IDsat or VT drift is acceptable or precision
analog where designers would cry about a 5% hot carrier
induced drift at 0 degC and the industrial guys are flat
out of luck at -40C where HCE can really go big.

Your degrees of freedom in designing a transistor for
Vds are channel length, gate oxide thickness, spacer
oxide chemistry & growth, and "drain engineering"
(halo and pocket implants, basically "poor man's LDMOS"
which get the digital folks the leakage they want
but ruin the transistor for analog / RF).

So there's your concise easy answer. I.e. neither.