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subthreshod leakage current problem

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lhlblue

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i have designed a current mirror with W/L=15u/20u m=1 to m=4, that is, a 4 times gain.
i use umc018 process. but my input current is very small, 0.5pA~2pA, then, i find that, when input is 0.5pA, the output is 20pA, when input is 2pA, the output is 26pA. it is not a 4 times amplification. it seems that, there is an additional 4.5pA leakage current((0.5pA+4.5pA)*4=20pA). the two MOS operates in subthreshold region(cutoff region in hspice), Vth=0.72V, the Vgs of MOS is about 0.35V.

1, what is the leakage current? is it subthreshold leakage? and is it Idb of MOS? how to plot Idb of MOS in hspice? is it like idb(MM1)?
2, can it be gate leakage? if yes, how to plot the gate leakge in hspice?
3, i see, in most technology lib, when current is small, such as, less then 10nA, the hspice model is inaccurate, is it right? can my lib be inaccurate here?
4, i see also, the optimal subthreshold region is in the range of -200mV<Vgs-Vt<0, is it right? why? for my case, Vgs-Vt=-370mV, can it not follow the exponential law in subthreshold region here?
5, the leakage will affect my circuit, and the amplification is not correct, how to remove the influence of leakage? or just because the hspice modle is unaccurate(if unaccurate, what can i do to amplify a 0.5pA current)?

thanks all.

Actually, first thing that I see in your case is pA is very low current. That the transistor is affected by leakage is quite normal, especially for 180 nm. I recall that if we talk about subthreshold region, vgs should be less than Vth, 3 or 4 times of Vt (Thermal voltage). If you rise your Vgs-Vt up to -100 mV, you probably acquire well mirroring. As you say, in subthreshold region there is exponential law. Thus, if you go down -370 mV for Vgs-Vth, probably transistor enter the cut-off, because the current diminishes exponentially for Vgs-Vth.

Actually, first thing that I see in your case is pA is very low current. That the transistor is affected by leakage is quite normal, especially for 180 nm. I recall that if we talk about subthreshold region, vgs should be less than Vth, 3 or 4 times of Vt (Thermal voltage). If you rise your Vgs-Vt up to -100 mV, you probably acquire well mirroring. As you say, in subthreshold region there is exponential law. Thus, if you go down -370 mV for Vgs-Vth, probably transistor enter the cut-off, because the current diminishes exponentially for Vgs-Vth.

i find another phenomenon, that is, the current ratio is related to vds of MOS pair, when vds of MOS pair is the same value, the current ratio is correct(1:4); with the increasing of vds difference of MOS pair(vds1-vds2), the current ratio becomes larger, from 1:4 to 1:40 or larger.
in my understanding, in subthreshold region, vds has a small effect on the current of MOS, so, i think, when input is 1pA or smaller, the MOS pairs don't obey the exponetial law, or not in the subthreshold region. however, how to describe the MOS behavior of input<1pA? and how to simulate it in hspice?

thanks.

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