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Recent content by leon

  1. L

    field programable analog device

    I am also interesting with such topic.
  2. L

    What to choose for DSP design? Xilinx or Altera?

    There is no big performance gap between alter and Xilin. You can select either. But, I think the xilinx has good document than @ltera.
  3. L

    What should a beginner do?

    I also recommend Active Hdl.
  4. L

    the clock of Xilinx Vetex2 FPGA?

    You can use 250M clk in vertix2p. But it is very hard. Maybe the floorplan should be done manully. For output 250M clk, you can see the PLL's descirpt in datasheet.
  5. L

    how i design LIFO on FPGA

    You can refer the FIFO design. I think it will help you. Or simply use a RAM to store the data, a counter to count the data number in RAM, you can make it work easily.
  6. L

    An overview of SystemVerilog 3.1

    system verilog itoa **broken link removed** An overview of SystemVerilog 3.1 By Stuart Sutherland EEdesign May 21, 2003 (7:09 p.m. EST) SystemVerilog is an extensive set of enhancements to the IEEE 1364 Verilog-2001 standard. These enhancements provide powerful new capabilities for...
  7. L

    New EDA consortium promotes assertion language

    New EDA consortium promotes assertion language By Richard Goering EE Times May 22, 2003 (4:10 p.m. EST) SANTA CRUZ, Calif. — Seeking to accelerate the adoption of the Property Specification Language (PSL) currently undergoing standardization by Accellera, 13 EDA companies have joined...
  8. L

    VHDL vs Verilog which more popular?

    verilog is a powerful language which can povide model at gate level. In Asic design, the verilog is used popular. In FPGA design, both them are used popula.
  9. L

    Handel-C and SystemC: could they kill VHDL and Verilog?

    system c, system verilog or handel-c Just as the conclusion in this paper, I think that it will need about 5-10 years that the high-level hdl can replace the vhdl/verilog.
  10. L

    Is OOP suitable for embedded system ?

    Currently, C is still the main-stream language used in embed system. Not the OOP. Because the OOP has so much overhead than pure C.
  11. L

    Instantiating a component in ISE

    In my option, the Xilinx provide better document and more fast device than Altera. But it is also more expensive that Altera's device. Both Stratix and V2p can fill the reqirment in application. The difference in speed only need to be taken care of when your chip usage is very high.
  12. L

    Instantiating a component in ISE

    Xilinx provides CoreGen. It has same fuction as MegaWizard in Quartus.
  13. L

    How can I use the QuartusII..?

    I have to say that there is no a book which include all the issues. You should read a verilog or vhdl handbook at first. And run some example on simulation to see how the hdl works. After that you can selecet some synthesisable IP core form web, implement it using Quartus or ISE. Xilinx's manul...
  14. L

    What is best tool to learn VHDL?

    aldec's active-hdl is a good tools to learn vhdl. After you is famlious with vhdl language, you should resort to synplify, modelsim, ise. Otherwise, the language is not useful. Because there is big gap between real design and pure hdl .
  15. L

    xnf file implementation - help needed

    xnf is the Xilinx Netlist Format file. It equal to the edf file. You can follow the edf flow.

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