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Recent content by latebloomer

  1. L

    how do we compute a signal's spectrum of an analog singal ?

    spectrum how do we compute a signal's spectrum of an analog singal ? What is the relationship between the signal's duration and sampling frequency?
  2. L

    calculate min clock period under different assumptions

    But in this case your timing path should be calculated from negedge to posedge like this: tPINV + tPFF + tXOR =< TW - tsu - T(high) TW - T(high) >= 54 TW >= 54 + T(high) why we need to count from negedge to psedge if we have the assumpations? Without assumpation and if without assumptions...
  3. L

    calculate min clock period under different assumptions

    t(high) = tPFF + tsu - tPINV where does this come from what i mean is youshould use Min tp INV instead of Max tp Inv to ensure your lowest thigh
  4. L

    calculate min clock period under different assumptions

    t(high) = tPFF + tsu - tPINV = 14 + 6 -12 = 8. I think you should use tpinv=2 in this case considering the path Q2-D3
  5. L

    calculate min clock period under different assumptions

    TW >= 54 + T(high) so when T(high)=0,we can have the maximum frequency.but is that possible? which means we don't have any high clock during each TW
  6. L

    calculate min clock period under different assumptions

    it's possible.Can you explain how is the clock period reduced if you increase low time to 80% by calualting the exact things?
  7. L

    calculate min clock period under different assumptions

    I don't know what is the relationship between %high clock with the minimum period. Disregard the 2 assumptions,i get. tPINV + tPFF + tXOR =< TW - tsu 12 + 14 +22 =< TW -6 TW >= 54 so what will change if we take the assumptions into account?
  8. L

    calculate min clock period under different assumptions

    so what will b e the difference between 1)and 2)
  9. L

    calculate min clock period under different assumptions

    Determine the minimal clock period TW for the following circuit. Use the following delay values for the flip-flops and gates. Flip-Flop: 5 ≤ tPFF ≤ 14ns; tsu = 6ns; th = 10ns Inverter: 2 ≤ tPINV ≤ 12 XOR Gate: 7 ≤ tXOR ≤ 22 1.Work the problem under the assumption that the clock is symmetrical...
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