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Recent content by knightnoor

  1. K

    Information regarding 70 mhz IF

    Thank you so much for your reply... please make few more points clear to me... Q)In case of 70 MHZ IF what is the bandwidth?
  2. K

    Information regarding 70 mhz IF

    Hello, Can anyone plz help me with my query....I wish to know what 70 MHZ IF actually means...i have been trying to google it but no satisfactory explaination was found... So i actually wish to know.. 1)What do we actually mean by 70 MHZ IF? 2)In case of 70 MHZ IF what is the bandwidth...
  3. K

    output width trouble in Vhdl programming

    Hi, I am a trainee and has been assigned the work to make a program in VHDL and have to run it in Xilinx ise ds. My program is like i have an architecture in which we have subtractor,multiplier,adder each 4 bit two input...now the output of each component is going into a multiplexer...and i...
  4. K

    Use of DSP blocks in FPGA

    HI, I am a Engineering final year student..and we are planning to make our project using FPGA...so i order to do so i need to do the deep study of FPGA...i have few querries regarding DSP blocks...i hope i will get help on this forum.... As i have already gone though few Xilinx PDF regarding...
  5. K

    .vhd file for xilinx ise ds

    can anyone help me...I need .vhd files for making ddc so that further i can call ip cores for dds and nco....so i need parent .vhd file to complete the ddc project...kindly guide me from where could i download such readly existing file...plz suggest any website from where i could download or...
  6. K

    [SOLVED] FFT core - Xilinx ise - This file cannot be synthesized

    Hi medra, It could be due to the reason that the kind of simulator you are using for the synthesis of the file is not compatible for it.
  7. K

    how to make a ddc using dds,nco,cic?

    can any one help me to make a ddc using xilinx ise ds 10.1 through ip cores....what exactly i want to know how to bring together dds,nco,cic in ip cores...i mean how to use these together to make a ddc...plz guide me...
  8. K

    Xilinx ise ds timing constraints

    Hi I am a beginner for software xilinx ise ds....I need help regarding the Timing constraints and the floor planning...can you please help me regarding the timing constraints that how to edit in the constraints editor and when would i know that the timing i have entered is the best for my...
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