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Recent content by kk_victory

  1. K

    vhdl code for pulse generation of pw=1ms

    pulse generator in vhdl Hi guys I have implemented vhdl code for generating a pulse of following specifications PW= 1ms i.e. 1ms=on & 1ms=off Means it is 50% duty cycle. entity pulse is Port ( clk : in std_logic; res : in std_logic; clk_div : out std_logic); end pulse...
  2. K

    vhdl code for pulse generator

    Hi guys I want vhdl code for generating a pulse of following specifications PW=1us, 1ms for PW=1us, 1us=Ton and 1us=Toff Means it is 50% duty cycle. I have implemented this code entity pulse is Port ( clk : in std_logic; res : in std_logic; clk_div : out...
  3. K

    vhdl code for pulse generator

    pulse generator vhdl hi venkat I have tried ur code but it is showing so many errors. bcoz i m using xiink ISE 7.1 some functions are not supporting. I m giving this how I implement in vhdl library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use...
  4. K

    Looking for a VHDL code for pulse generator

    Hi everyone I m new comer in Vlsi Field I want to generate pulse of PRI=1KHz and Pulse width + 1µs. So I need Vhdl code for Pulse generator Pls let me favour. Bcoz I have to complete this project in Short time. thanks Kamlesh
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