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Recent content by kilone

  1. K

    phrack59 - Unix/Linux security

    Hope it helps the guys in need.The rar file
  2. K

    about redhat advanced server!!

    Hope it helps the guys in need.The rar file
  3. K

    INFO: RH7.2 & Pentium 4

    Hope it helps the guys in need.The rar file
  4. K

    PlanAhead - Hierarchical Floorplanning

    What about Synplicity's Amplify? Which one is better? or do we need to use both of them in our future Huge design?
  5. K

    Audio Processing for PC ?

    Hi, matrixanov: Thanks for your reply. What I really want to know is the audio processing algorithm used for the Sound Card. You know that sound cards used in PC are usually PCI based, but I'm now designing an embedded system which may use no PCI bus. The functionaility of audio signal...
  6. K

    Audio Processing for PC ?

    Hi, all: I'm a newbie to audio processing. Does anyone here know about the audio processing algorithm used for PC (like in the Sound Card for example) ? My current task is to decode the audio information coming from the internet or local harddisk and then send the decoded bitstream to a...
  7. K

    down-sampler & up-sampler

    Yeah, I think they are linear.
  8. K

    DSP with FPGA: Verilog or VHDL ?

    But high-level language tools often provide unefficient RTL code, please refer to www.fpgajournal.com for the article - "Leading Languages - Is There a Future Beyond RTL"
  9. K

    avalon to wishbone bridge

    It's said in topic that Altera has made this design, but I cannot find any information on Altera's Website.
  10. K

    RDP - Remote Desktop Protocol ?

    Does anyone here have experience on RDP implementation?
  11. K

    About NIOSII and General Purpose CPU ?

    I want to try NIOSII in my new embedded design. According to Altera's announcement, NIOSII can provide up to 200 DMIPS performance(in coming Stratix2), and we also know that there exist abundant hardware resources inside FPGA devices(Registers, High Speed Buses, IPs, etc.), which will make most...
  12. K

    Problem with Xilinx DCM and FSX output

    dcm xilinx low frequency mode Yeah, 24MHz, Even I am using 24.576MHz clock input, my FSX outputs are sometimes stable, sometimes not. That's the real story of mine! If your input can only be 9MHz, I think you can try Altera's PLL...
  13. K

    How to avoid glitches at the non-registered output?

    Can glitches be avoided? So try to use sync design everywhere(as much as possible) in your project. Most glitches are very 'short' time length so that SETUP/HOLD time requirements cannot be satisfied. Therefore, glitches in sync circuit will be filtered and will harmless to your design.
  14. K

    who may tell me what is the diffence between dsp and fpga ?

    In one word: FPGAs provide high speed logic, and DSPs provide flexibility of control
  15. K

    Which tool is the best for FPGA programming & optimisati

    Which FPGA s/w is good? 3 FPGA IDE s/w: Xilinx ISE: Mature, Stable, Efficient, Best Online Support Altera Quartus: Stable, Efficient Lattice ispLever: Newcomer
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