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When the signal level rises above a certain high threshold, the system switches to a high state, and when the signal falls below a certain low threshold, the system switches to a low state. The key point is that the high and low thresholds are not the same – there's a region of uncertainty...
I had considered DE2i-150 FPGA Development Kit. It uses Cyclone IV EP4CGX150DF31, and has 149760 LEs. I am not sure abut the "LE area" of this FPGA. The specification just list the 60nm. Will that be the LE area?
I have designed an IP, which I want to implement on an FPGA for testing purposes. The design has been synthesized and meets all constraints. How do I find an FPGA that would have the required logic elements to fit this design. Is there some math that I can do to figure this out.
The area report...
I have 2 similar analog blocks which output a single bit signal. The signal from Block A is not related to the signal from Block B. Before using the signal in my sequential logic, I have synchronized each separately using a 2DFlipFlop synchronizer. CDC checking tools complain that this is a...
This is a general question, and can apply to any micro-controller.
If I have a pin configured as output and connected to an led, how can I prevent the led from turning on briefly when the uC is turned on or reset. As the uC turns on (or is reset), all the pins are high, and then it starts to...
I am trying to interface AT45DB161E chip with LPC1758. I want to read the first 528 bytes from page 0. According to the datasheet if I want to directly read a page from the chip then I have to issue the opcode 0xD2 followed by 24bits which includes page address and byte address
In my code this...
I have a Xilinx Zybo board. I followed the tutorial here and was able to create my own IP (simple multiplier) and got it connected to the ARM processor over the AXI-Lite bus. I want to do the same thing over AXI-Stream bus so that I can continuously send inputs and get outputs from the...
I am designing a 9-Tap FIR filter, I have used MATLAB to get the filter coefficients
-0.0041 0.0077 0.0893 0.2433 0.3276 0.2433 0.0893 0.0077 -0.0041
I have multiplied all the coefficients with a scaling factor to scale them to 16bits. The input to the filter are random...
I am designing a UART using SystemVerilog, the interface has been provided
interface u0if ;
logic clk,rst;
logic read; // bus read operation
logic [7:0] addr; // device address
logic [7:0] din; // bus data to UART
logic write; // write operation
logic [7:0] dout; // bus...
I came across a verilog example of improving power consumption in a multiplier. The original code is
reg Enable;
reg [31:0] A, B, DataOut, MultOut, AddOut;
wire [31:0] A, B;
always@(posedge clock)
if (Enable == 1) DataOut <= MultOut;
else DataOut <= AddOut;
assign MultOut = A * B;
assign...
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