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Recent content by kenleigh

  1. K

    [SOLVED] How to link output of PLL to ODDR2?

    Thanks for the help. I will figure out the equivalent in Verilog. Many Thanks!
  2. K

    [SOLVED] How to link output of PLL to ODDR2?

    Thank you for the answer and the uploaded snapshot however I'm sorry I did not understand what you intend to show me using that? should I modify my code like this in the PLL instantiation I will change .CLK_OUT1 (clkout_buf) I would add a not gate also not not1(clkout_buf_n...
  3. K

    [SOLVED] How to link output of PLL to ODDR2?

    Do I have to add a not gate at the input of the ODDR2?
  4. K

    [SOLVED] How to link output of PLL to ODDR2?

    My top level module looks like this module clkgenerator ( CLK_INP1, CLK_OUTP1, RST, LOCD); input CLK_INP1, RST; output CLK_OUTP1, LOCD; // INST_TAG clk_wiz_v1_5 camclk (// Clock in ports .CLK_IN1 (CLK_INP1), // IN // Clock out ports .CLK_OUT1...
  5. K

    [SOLVED] How to set output pin state of a module?

    Many thanks that helped immensely.
  6. K

    [SOLVED] How to set output pin state of a module?

    Thanks again for the wonderful examples. In this code snippet you have set RESET and PWDN in the initial block and then in the always block you keep setting it at every positive edge. I guess you used the always block to make this module synchronous, right? otherwise even the initial block...
  7. K

    [SOLVED] How to set output pin state of a module?

    Thanks for the explanation. That sure was helpful. What about "=". That sure should have worked, shouldn't it? And you said that the "assign" keyword does a continuous assignment, does that mean it does it at every clock cycle or only once at power up?
  8. K

    [SOLVED] How to set output pin state of a module?

    Yes! this works, however I'm unable to understand what was the problem with "=" and "<=". Why didn't they work out? Many thanks for the tutorials!
  9. K

    [SOLVED] How to set output pin state of a module?

    Even using <= gives me error. It says, Syntax error near "<="
  10. K

    [SOLVED] How to set output pin state of a module?

    I'm a noob in verilog. I have a module that has 2 outputs, RESET and PWDN amongst others. I want to make RESET output high level(3.3V) and PWDN output low level (0V). In a microcontroller I would have done something like this RESET = 1; PWDN = 0; Can I do similar in Verilog , something like...
  11. K

    Few questions regarding SCCB protocol?

    Anyone out there? who has done some work on SCCB? :(
  12. K

    Few questions regarding SCCB protocol?

    As any one here successfully implemented the protocol? 1. Is it very similar to the I2C protocol? 2. Are pullups required on the SDA pin, the SCCB spec doesn't state anything about pullup's? 3. Do I need to tri-state the SDA pin to read the ACK from slave, SCCB spec calls the ACK as NA or...
  13. K

    [SOLVED] How to use bidirectional IO, need it for I2C?

    In fact the 'sda' pin is acting as a transmit sometimes and a receive sometimes, at the moment I'm trying to implement an I2C master, not quite sure what you mean by "receiver module"?
  14. K

    [SOLVED] How to use bidirectional IO, need it for I2C?

    Many thanks, will try this one out and keep you posted!! ---------- Post added at 19:20 ---------- Previous post was at 19:18 ---------- the write_enable is of datatype reg, right? and I have to manually set or reset this bit when I am doing reads or writes, right?[COLOR="Silver"]
  15. K

    [SOLVED] How to use bidirectional IO, need it for I2C?

    Thanks for the link Alexium and for the expert tips FvM. From the point of view of the bidirectional pin question, what should I do now? I mean is something like "inout sda" the way to go? and then how do I assign sda inside procedural blocks, since the compiler doesn't allow net data types to...

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