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Recent content by kbkdec15

  1. K

    How to integrate C program to verify ARM based SOC in UVM testbench?(using Questasim)

    Hi Every one , Please help How to drive my C programming simulation into ARM core and How to integrate the UVM testbench to ARM SOC for functional simulation. I am using Questasim tool . Let know any reference documents, videos or any source to learn Very thanks in...
  2. K

    How to get 100% statment coverage and not 100% brach coverage?

    Thank you dave.
  3. K

    How to get 100% statment coverage and not 100% brach coverage?

    hi every one ,m Please let me give one example for my question? thanks kbkdec15
  4. K

    How to handle "Range must be bounded by constant expressions" error in Verilog or ?

    How to handle "Range must be bounded by constant expressions" error in Verilog/SV?? i have gone through various forms and articles . i am not getting proper solution . please help me ?
  5. K

    baud rate calculation

    Why should we multiple with 16 only ? what is logic using 16 here .
  6. K

    what is the advantage of exclusive access in AXI?

    HI krishanu , have you got complete concept about Exclusive Access. Please clearify me about Exclusive access. please update this topic
  7. K

    Doubt on blocking and non_blocking statements ?

    following two set of statements are result same. set1: fd1 =$fopen("binary.txt","r"); fd2 =$fopen("binary.txt","w"); fd3 =$fopen("hex.txt","r"); fd4 =$fopen("hex.txt","w"); set2: fd1 <=$fopen("binary.txt"); fd2 <=$fopen("binary.txt"); fd3 <=$fopen("hex.txt")...
  8. K

    ASIC Design Flow ? please clarify my confuse ..............?

    hi maulin sheth , thank you very much. i will follow your guidelines regards kbkdec15
  9. K

    ASIC Design Flow ? please clarify my confuse ..............?

    hi maulin sheth, thank you. generally what we will do in pre-synthesis and post synthesis. i think ,To get 0->1 or 0-> transitions , should apply for some pattern only. how STA is differ from DTA ? Regards kbkdec15
  10. K

    ASIC Design Flow ? please clarify my confuse ..............?

    Hi rca, thanks i have heard about various words like pre synthesis , post synthesis , pre validation and post validation. but i do not know when they would come in design flow . please can you explain those words and related information regards kbkdec15
  11. K

    Creating library in verilog and mapping library ?

    hi , how to create library in verilog ? i have seen LRM there is "library" keyword, how could it useful ? thanks kbkdec15
  12. K

    ASIC Design Flow ? please clarify my confuse ..............?

    HI everyone , when will Pre synthesis and post synthesis come in ASIC Design flow? when will Pre validation and post validation come in ASIC Design flow? why should we need pre and post (synthesis and validation ) ? what is difference between validation and testing ? when...
  13. K

    In UART Design , sending stop bit

    thanks @amitjagtap, i got analysis.
  14. K

    Questasim tool Download link ?

    hi rudra, thanks . is there any alternate process to uvm . or please let me know, is there any other free tool ? thanks kbkdec15
  15. K

    Questasim tool Download link ?

    please can anyone provide me link to download the questasim tool which supports UVM. I think later versions of questasim 10.1c will support UVM . advance thanks kbkdec15
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