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Hi everyone,
I am trying to insert a scan chain to a digital block containing serial interface, registers and io programmable, etc. The package pin is scan enable signal whereas the scan in scan out and scan clk are all generated within (by muxing the serial inputs). When I do the compile -scan...
how to test cmrr amplifier
hi boooser,
When you monte-carlo on differential op-amp it gives the common-mode gain variation and mean. Do a separate simulation for differential gain (say at worst corner) and take the ratio. I guess this is a crude of doing but it gives a good estimate of worst...
Hi,
The note Lcurrent-source=Lcascode maybe insisting on keeping the L(M4)=L(M2). Typically, the cascode transistors are sized bigger i.e W/L(cascode)> W/L(current-source). General practice is to keep L(current-source) >L(cascode).
regards
Re: help for ADC design
Hi,
melc, for your kind information please refer this site which gives the procedure to find the harmonic distortion. If you go by this calculation, sampling frequency cannot be integer multiple of input frequency. This is a standard procedure followed.
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comparator resolution simulation
Hi,
To your first question....if your reference voltage is VDD then your comparator design would be very difficult because when the input voltage of comparator is Vdd , preamps go into linear region while the other input is sitting at Vdd/2. Instead a simpler...
Hi Crusader,
If u still havent solved the problem...then try checking for systematic offset in op-amp. The DC sweep is typically the curve one would obtain if the systematic offset is not zero. Also, the DC curve you have shown is swept from negative range...when the supply is single (Vdd) how...
Hi,
For finding the mismatch in MOS transistors, Vth mismatch is the major concern as far as I know. This can be found out theoritically by using the relation, sigma=Avt/sqrt(W*L*M) where M is the number of fingers. This is 1σ mismatch...so depending on ur design window u can choose like ±3σ...
Re: How I can Simulate Fully diffrential Folded cascode OP A
a proper technique is to connect the circuit in feedback with unity gain and apply input signal at one end and observe the ac response ....
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regards
hi
I agree with Kral...its the problem of current drive capability. One way to overcome the problem is to design for a low output voltage within the op-Amp's voltage vs current curve. Then use a second op-Amp stage to improve the gain and obtain the required output voltage.
regards
Refer Razavi's book ...it explains switched caps in good detail. Also Baker Lee's Mixed signal circuit design covers switched cap in great deal.
regards
hi
when designing the current mirror you have to first decide the range of Vgs and W/L...ie upper and lower limits from the current eqn.
Next, from the given threshold variation of the MOS transistor decide the values of these two parameters optimizing for smallest area and smallest variation...
lecture on adc design
hi
i presume that you already had course in analog ic design and cmos concepts. then, read the chapter on ADCs in p.allen book. first understand the different architectures in ADCs....know the diff blks in your concerned architecture and then study each blk in detail. For...
i had this question in mind for a long time...
is analog ic design moving at the same pace as digital? sometime back i read in an article that analog companies still continue to make chips in 0.13u and 90n....can analog design be scaled so quickly as digital? like Intel which is now looking at...
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