What about the future of the Analog layout designers?

[vijay.kumarreddy]

Hi all,

I'm working in analog layout design.But i came to know that in 90 and 65 nanometer technology designers themself prefer to do the layout also.Is it true?

Can anybody address this ....

vijay

 

[carpa]

Dont worry about it. Analog layout is a time consuming job, which is not preferred by analog circuit designers.

 

[Karthikeya]

i had this question in mind for a long time...
is analog ic design moving at the same pace as digital? sometime back i read in an article that analog companies still continue to make chips in 0.13u and 90n....can analog design be scaled so quickly as digital? like Intel which is now looking at 45nm technology.

 

[darkk]

I guess that when the silicon scales down, the digital guys will have to join with the analog communicty somehow. For analog guys the change is that so tough, since the fet's length don't need to scale down that much as in digital ckts.

 

[centiago]

I am beginner in this field. Just got couple of books to kick off, can experts guide me how to go about.

Do I have to start with analog & then learn digital, or both are different fields?

Thanks in advance.

 

[laglead]

In my opinion. analog insight is fundmental for both analog and digital circuit designer (not for logic designer). But designing analog and digital need different consideration. It is not a good idea for beginner to study one first and the other next. Take them both!

 

[matchasm]

i had this question in mind for a long time...
is analog ic design moving at the same pace as digital? sometime back i read in an article that analog companies still continue to make chips in 0.13u and 90n....can analog design be scaled so quickly as digital? like Intel which is now looking at 45nm technology.

The problem is exactly this. Analog design is more difficult for lower voltages, because the threshold-voltage of a transistor does not scale with supply voltage.

Making an analog circuit for a supply voltage any lower than 3V is extreeeemely difficult. It is actually quite amazing that some people seem to be able to do this for 0.9V. Try stacking cascodes at such voltages!

Digital engineering is becoming more interesting, because noise, heat and all that stuff starts becoming more dominant. I read the January JSSC and besides the new Cell processor for the Sony PS3, which includes some pretty nifty temperature sensing schematics, there is an interesting article about supply voltage dithering for different temperatures.

 

[mithlesh]

The opeting supply voltage depends on design to design. Some designs can easily be implemented with lower supply, even 1V.
The analog designers take care of technology scaling by keeping channel length greater than 1um. So even, one works in c90/c65/c45 technology, short channel effects are not severe.

Though analog layout is time consuming job, but its got challenges and its fun doing that.

regards,
Mithlesh

 

[montage3000]

the critical block should do themself, but general block still need you