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Recent content by kamalkundu

  1. K

    Why do we need to sample USART input ?

    Why do we need to sample (mostly 16 times) the input to USART? as we don't need it for other protocols like SPI.
  2. K

    Verification plan for cache architecture ?

    Can somebody give some guidance (links to read) on verification plan for a cache architecture? Let it be signal processor cache so that we need not worry much about cache coherence ?
  3. K

    Verification test sequence Vs Chip start sequence !

    I am working on micro-controller verification where we are using assembly (for processor) and verilog to give stimuls or probe the value. When somebody asks me about verification test sequence.I come-up with answer that : 1) Chip is power up and power on reset is de-asserted. 2) Reset sequence...
  4. K

    problem with assign in verilog

    I also tried with vcs and did not found any problem and I also did not see any change after synthesis. its remains 2-input AND.
  5. K

    problem when i write veriog code in pmos and nmos switches

    can you write the code (or part of the code) which is giving trouble ?
  6. K

    [SOLVED] Is anybody worked on Scripts?

    Yes I usually work with Perl.
  7. K

    x-propagation and z-propagation in digital system design

    x-propagation happens because of unknown values at the port or any intermediate register. One of the goal of post-layout simulations is to check whether there are any x's propagating even when ports are given Low or High.
  8. K

    what is Brown-out and black-out detctor ?

    Thank you very much ckshivaram ! Have a nice day !
  9. K

    what is Brown-out and black-out detctor ?

    What is Brown-out and black-out detector?
  10. K

    report_case_analysis in RTL Compiler

    Hello , How can I report case_analysis in RTL Compiler? I am looking for something similar to REPORT_CASE_ANALYSIS used in DC Thanks
  11. K

    cdn_loop_breaker in Formality

    I have generated a netlist using Cadence RTL Compiler which introduces cdn_loop_breaker wherever it breaks the combinational loop. Now I am using the formality for formal verification but Formality does not understand these "loop breaks". Do we any option using which Formality will be able to...
  12. K

    ungrouping certain hierarchies (RTLC loop issue)

    I am ungrouping certain hierarchies in my design. I have written a small tcl in RTLC to do so: Suppose I have a design $Top, having hierarchy as follow: $Top - A (Inst name: i_A_inst) - B (Inst name: i_B_inst) - C (Inst name: i_C_inst)...
  13. K

    Migrate "generate statements" from DC to RTLCompil

    Hello, We are migrating from DC to RTL Compiler(Cadence). Design engineers have used generate statements exhaustively which were easily understood by DC. But I am wondering how can we utilize same verilog code (with generate statements) in RTL Compiler. code example...
  14. K

    Getting illegal redeclaration. [vlogpt-22]

    I am migrating from DC(Synopsys) to RTL Compiler (Cadence) and I am geting "illegal redeclaration. [vlogpt-22]" error as I have been using `include command to ease the simulation .Please let me know any solution so that RTL compiler can work with same HDL code.
  15. K

    synthesis multiple modules in Xilinx WebPack

    Hello, I am facing exactly same problem. Please let me know how you solved this in your case. Thanks.
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