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Recent content by K4R1

  1. K4R1

    [SOLVED] "PSUB" pin in HV 0.35 µm AMS

    Yes, indeed. I found a solution, just erase that pin and connect the well where you find it most convenient electrically ! Works just fine !
  2. K4R1

    [SOLVED] "PSUB" pin in HV 0.35 µm AMS

    Hello, I just found a strange pin within the schematic of an isolated low voltage "nmosi" transistor called "psub", what does it mean ? Where and what is that pin ? Thanks for your help ! Karl
  3. K4R1

    [SOLVED] Annoying void space in layout

    Pasted and copied the layout in a new cell file, works fine !
  4. K4R1

    [SOLVED] Annoying void space in layout

    Hello, How could you make layout XL "focus" only on the layout and not some extra space around the layout ? The thing is that when i generate my cell, it creates a larger cell than it should be because of an "extra" space added i don't know why ! There is no floating pin nor any other object...
  5. K4R1

    [SOLVED] Strange mismatch between layout & schematics (AMS 0.35 HV)

    Ok, i solved it... It was very tricky but obvious. You can't pin "mosN20t" with "mosi20t" !! So to fix this, i simply separated the bulk polarization and joined them where it was needed. Have a glance at the image enclosed to the message...
  6. K4R1

    [SOLVED] Strange mismatch between layout & schematics (AMS 0.35 HV)

    Ok, I'm looking at it right now... Besides, what's the purpose of the "psub" pin ? Where it should go ? It seems to make me short cut wherever i pin it.... Thanks for your time
  7. K4R1

    [SOLVED] Strange mismatch between layout & schematics (AMS 0.35 HV)

    Hello, Routing some nmos20t in 0,35 HV, i got a very strange parameters mismatch between the layout and schematic, where there should be none. My LVS error report tells me that their is a mismatch of 20% which is completely impossible since the schematic transistor and layout transistor have...
  8. K4R1

    [SOLVED] DRC issue in AMS 0.35 µm HV

    Re Hello, I have an other question related to the layout of an isolated MOS. Actually, i am trying to route the two transistor circled in red and connect the diode linked on the bulk. But i do not understand which part of the blk connection i am supposed to connect to my high voltage so the...
  9. K4R1

    [SOLVED] DRC issue in AMS 0.35 µm HV

    By the way, i was wondering ,what is the physical explanation for having a RPTUB ring outside a DNTUB ? Why is an HV MOS not like a regular MOS in 0.35 µm ??!
  10. K4R1

    [SOLVED] DRC issue in AMS 0.35 µm HV

    Ok, i got it ! Actually, here is how i solved the problem: Draw a "ndiff_rptub" guard ring around the transistor with the automated ring creator in Layout XL. Solved my issue ! Many thanks for the help !
  11. K4R1

    [SOLVED] DRC issue in AMS 0.35 µm HV

    Many thanks for the reply. Actually, does it mean that i have to draw a PD_N via around the transistor and draw a SNTUB around it ? What are the layers used to draw the NTAP ? Thanks for your time.
  12. K4R1

    [SOLVED] DRC issue in AMS 0.35 µm HV

    Hello all, I have 2 DRC errors that i do not understand in my layout. I am actually routing a very simple inverter but using a HV NMOS, with a protective diode on the bulk. And since the layout of this transistor do not looks like the one we have usually when we use a common HV MOS, i am a bit...
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