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My recommendation is to not make a top level that is different between synthesis and simulation. Without an accurate simulation model of reality, then debug of real world problems can only be done on hardware which is not efficient.
What is the problem with creating a simulation model for a...
Add "-wlf <filename>" to the vsim command to specify the .wlf file location.
Type "vsim -help" to see a list of all the options that are available. Or type "vsim" and it will pull up the GUI which lets you specify the various options.
Kevin Jennings
The maximum rate will have more to do with other decisions that you've already apparently made rather than PCB effects. Some things that you appear to have decided that will hinder high throughput:
- A parallel bus rather than a SERDES interface
- Not using a source synchronous interface to...
The people to answer the question of 'Why' would be the ones who created the numeric_std library...which was released 23 years ago. They have probably long since moved on. Consider using the fixed point package instead which does extend bits as you are expecting them.
Kevin Jennings
To compare numbers you simply use the less than operator (i.e. if a < b then...). If that approach meets your timing requirements, then you're done. Don't make it harder than it needs to be. If performance is not met then break the comparison up into a comparison of two 32 bit numbers where...
My first choice would be have the board route the clock and data to both the FPGA for input and whatever the other device is that needs to receive the signals. That is the best way to preserve whatever timing relationship that currently exists.
I'm assuming that the FPGA has some actual need...
I don't think so since there is no relationship in the FPGA design between IN_CLOCK and IN_CONTROL. The tools should probably generate a warning saying that the constraints you listed were ignored.
Kevin Jennings
I'm not sure, but I don't think the tool will do anything. If you have a hold time issue, the problem is with your design because you have most likely used an internally generated clock based on logic or you have a clock domain crossing.
If you use a synchronous design technique rather than...
The 'report' statement is what you would use. While 'report' is typically part of an assert, it can standalone as well. The only drawback there is that report on it's own must be used within a process while assert can be concurrent. As for converting the state to a text string, you would...
To simply accomplish the function, then the VHDL-2008 functions are the way to go as TrickyDicky posted. From the 'provided me with a way to practice certain aspects of my VHDL skills' perspective, I would make the following suggestion:
- Make your functions work with any size vector. That...
This suggests that slv is not defined correctly. It should be defined as a four bit vector in the interface rather than as an unconstrained vector.
Kevin Jennings
For constructing the name of a file to read or write from the testbench
But there are packages that do exactly that
After you've read in something from a text file that you would like to use in your testbench.
Using image in report statements is probably the most common usage. Although not...
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