Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

What is the application of the 'image and 'value attribute in VHDL?

Status
Not open for further replies.

matrixofdynamism

Advanced Member level 2
Joined
Apr 17, 2011
Messages
593
Helped
24
Reputation
48
Reaction score
23
Trophy points
1,298
Activity points
7,681
The 'image attribute in VHDL returns a string for certain types. The 'value attribute is opposite to the 'image attribute. Correct?

(1) The 'image attribute can be used to print value of certain types to transcript using report command. What else would it be used for?

(2) Why does 'image attribute not exist for std_logic_vector? That makes no sense at all.

(3) When would one need to use the 'value attribute?
 

Why not read the VHDL language reference? It tells that IMAGE and VALUE attribute can be applied to scalar types and its subtypes. Std_logic_vector isn't a scalar, it's a bit array.
 

(1) The 'image attribute can be used to print value of certain types to transcript using report command. What else would it be used for?
For constructing the name of a file to read or write from the testbench
(2) Why does 'image attribute not exist for std_logic_vector? That makes no sense at all.
But there are packages that do exactly that
(3) When would one need to use the 'value attribute?
After you've read in something from a text file that you would like to use in your testbench.

Using image in report statements is probably the most common usage. Although not entirely the case, whether you use image/value a lot or a little seems to depend on how much you like to interact with external text files in your testbench. So, in the end, it's one of those 'handy some of the times' things more than something that you use a ton.

Kevin Jennings
 

What package coverts std_logic_vector to hex and which package can return a string representing hexadecimal equivalent for a std_logic_vector?
 

What package coverts std_logic_vector to hex and which package can return a string representing hexadecimal equivalent for a std_logic_vector?

In VHDL 2008, the std_logic_1164 package.
Pre 2008, the std_logic_textio package (its non standard, but included in all simulators).
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top