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Recent content by jy0908

  1. J

    [SOLVED] [PrimeTime(STA)] Why transition time is "0" in my design?

    Problem solved. It was due to wrong sdf file. Thank you.
  2. J

    [SOLVED] [PrimeTime(STA)] Why transition time is "0" in my design?

    Hi. All, I have one question about my PrimeTime results. To see the timing reports of gate-level design, I ran the PrimeTime. The results of the command ("report_timing -transition_time ......") is as follows: *********************************************************** Startpoint...
  3. J

    To make netlist have the same reg names as those in verilog code

    Hi. RBB, Oh I see. I really appreciate it :) The code you gave me works well when I change my code as you suggested. Thank you so much
  4. J

    To make netlist have the same reg names as those in verilog code

    Hi. RBB, I really appreciate it Could you let me know which version of DC you did you use?
  5. J

    To make netlist have the same reg names as those in verilog code

    Oh. I've already used both "read_verilog" and "analyzed-elaborate" for the synthesis. But, it doesn't work. :( Anyway, thank you very much. By the way, why does the optimization occurs in verilog read step? (I've checked the reg names are changed after reading source file)
  6. J

    To make netlist have the same reg names as those in verilog code

    Hi. RBB, I got these Warnings and Errors when I put suggested "set_dont_touch" codes in my verilog source code. I think it is because... as soon as DC reads the verilog source code (such as read_verilog), it changes reg name in advance to synthesize it. *********************************...
  7. J

    To make netlist have the same reg names as those in verilog code

    I have some question about synthesis. My question is that: Is there any way to keep the reg name during the synthesis? I would like to give an example of my verilog source code. :) In this code, I uses 4 regs: 'mem_read_data_r', 'mem_read_data_valid_r', 'mem_load_rd_r', and 'daddress_r'...
  8. J

    Hold Time Violation during Gate level simulation

    Thank you :) Unfortunately, It is a fully synchronous design, has only one clock domain, no muulti cycle and false pahts, and no clock drivers.
  9. J

    Hold Time Violation during Gate level simulation

    Hi. All, Could you guys help me understand this? I have some hold time violations when I do gate level simulation of my design. The problem is that - No violatins when I use 100ns clock cycle time; always #50 clk = ~clk; - Hold time violations when I use 10ns clcok cycle time; always #5 clk...
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