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Hello,
What is the advantage of separating the analog ground from the digital ground in the IC design when in the PCB I am going to connect them to the same ground potential? I mean by end they will be tied together.
Thanks
Best Regards
Dear friends,
Thanks for the reply and explanation,
So how the the confidence level that you select will determine the sample size required in your model?
Can you please explain that in steps, it will be really helpful.
I have tried to set the confidence level to 99% using initial size of...
Thank you friends very much for your reply,
Now I got it,
The length and width is definitely what you have to pay to achieve regardless of the used technology,
However, the minimum size rule of thump of 2 X L of the used technology is not about reaching an absolute value of length or width...
Thanks freebird for your reply
:D, I understood that
but what about my second question :)
always in analog circuit advised to work at least twice the channel length of the node technology, is that relevant to the uncertainty of the fabrication resolution to reduce the amount of error?
Thanks freebird for your reply,
If my target specification requires minimum L= 1 µm for example which meets the specific design metrics, Also suppose in the design I have High aspect ratio with transistor width say 250 µm. Such design is implemented with 0.35 µm.
Now what is the point of being...
Hello,
I use technology 0.35 µm, but in analog design I usually for better performance I fix the length to 1 µm.
Now we want to move to 90 nm, and I see many people fix the length to 200 nm.
Now if 200 nm is ok for 90 nm technology, why then we use 0.7 µm or 1 µm in the 0.35 µm technology...
Hello,
I have a large differential sensor signal of 0.5 Vp-p. I use an ADC of 14 bits with full-scale voltage of 2 Vp-p. Therefore I set the gain of the instrumentation amplifier (In-Amp) to 4 to utilize the full dynamic range of the ADC and thus achieving the highest resolution of 14 bits...
thanks for the reply,
let start with the small capacitor unit of 50 fF.
Now you suggested that MOS switch resistor should be considered, I agree. However, in order to reduce the switch resistor, this requires to increase the switch ratio, which in turn increase its parasatic capacitor and...
Hello,
I am using MOS switch for controlling bank of capacitors.
The capacitor bank is a binary weighted array start from 50 fF, 100fF, 200 fF, 400 fF, 80 fF, 1.6 pF,
These capacitor represent the compensation capacitor for my op-amp toward bulding programmable bandwidth amplifier.
Coming...
Thank you once again, friends,
I am near to understand it but not completely,
The technology I am using support both 3.3V and 5V CMOS main modules.
As you also mentioned before, I can use the 5V modules and supply the circuit with 3.3V taking in to consideration the threshold voltage of the...
Dear friends,
Thank you very much for your answers and nice explanation you provided me.
Yes the 0.35 µm technology I am using it supports the 5 V I/O,
But the core module is still 3.3 V, so do you mean that 5 V I/O pads will clamp the 5 V to 3.3 V ?,
Thank you
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