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Dear all,
Recently I am trying to synthesis a large module with both Automated Chip Synthesis (ACS) method and traditional top2down DC Ultra method. Then, I compared the synthesis results for both two methods. I found the ACS gives a very large area report, say 70% more than top2down DC Ultra...
system bandwidth calculation
We are designing a SoC for multimedia purpose, and many times i am confused on the system bandwidth. Let's say, one system with one CPU, one DSP, LCD controller, and SDRAM, to implement a MP3, MPEG-4 player.
Could someone show me how to do the bandwidth...
random data generator vhdl
Dear All,
Can someone provide a solution to implement a random data genertor in HDL (the seed will be provide by s/w as input)? The code should be synthesisable.
Thanks a lot!
Re: Help wanted! What doest the "memory mapping" m
NITU, thank u so much!
I marked ur reply as helped. Meanwhile, I want to clarify one thing: how could a memory be multiport? If we mapped all the memory blocks into one memory, this should have be a single port or dual port one, right? Could u...
when we do the SoC design, I always hear the word "memroy mapping". now we have a case that all the memories in the SoC are mapped into one memory, and it includes h/w registers, stack, interrupt vectors, and code rom, etc.This memory has the sequential addressing.
Right now I have the...
i just finished the initial synthesis for a CPU subsystem, and i got an area report. from the report, how can get the basic gate-count info?
can someone give a detail explaint. Thank alot!
I read one paper on the H.264 decoding, and one sentence says: "Using a typical PDA processor, e.g. the Intel PXA270, the required frequency for H.264/AVC decoding for DVB-H is about 420 MHz. (320x240 pixel resolution, 384 kBit/s)"
Can someone tell me how to reach this conclusion? why the...
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