Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Re: verilog doubt
I think you are refering to the delay involved in generation of seqfound signal.
previous<={previous[1:0],data};
seqfound<={previous==pattern_searched_for};
When you change the value of previous signal, this value is available to seqfound expression in the next iteration...
Re: State Machines.
I think that using 5 state machines will give a higher speed of operation compared the other alternative. However, one needs to be careful while coding 5 state machines. But, if you want higher speeds, the implementation of state machine on BRAM is the other alternative.
unsynthesizable constructs in vhdl
you do require some knowledge of unsynthesizable codes for verification purposes... any vhdl book as such doesnt separate out the synthesizable code and concentrate on them.. you need to have a knowledge of both.
DSP on FPGA
Hi,
I am want to start implementing DSP ckts on FPGA. I am famlier with VHDL/Verilog, but have no idea how to go about in implementing filters, MACs etc...
Any suggestions about any sites or materials?
thanks in advance
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
