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Recent content by jluhzw

  1. jluhzw

    what's wrong in my setting about ultrasim in cadence

    When i do the ultrasim in cadence. I want to save the point information with this option "usim_save file="/home/temp/tt" time=1u repeat=2m but we run, it reports the error. I make sure the directory is correct and can write the file in my directory. Do you know what's in my setting as...
  2. jluhzw

    How to speed up the Hspice simulation?

    Re: hspice speed up Hi Could you please explain detail how to reload the saved opearting point in Hspice. Thanks !
  3. jluhzw

    Why a I overshoot when CC to CV mode in linear bat charger

    Could you share your experience here? It will be very nice for you!
  4. jluhzw

    Analog CMOS parameters calculation

    cmos cgd you can find the mobility(u) from model file by the parameter (u0) and threshold voltage by the parameter VTH. also you can calculate the Cox by the parameter TOX in the model file following the equation Cox=3.45fF*(100e-10)/TOX. Generally, you can calculate the gm as the equations...
  5. jluhzw

    LDO (Low drop out regulator )

    ldo(low drop-out) 레귤레이터란 Firstly, you can simulate loop with the H_SPICE to see there is enough PM then, you can test its stable by the transient load step from light load current to heavy load current or from heavy load to light load.
  6. jluhzw

    How to find out the leadage current?

    Dear All If there are any hints to find out which device has too much leakage current in my project when the tool is the H_spice. As far as I consider, I will firstly find out which block consume too much leakage current and then push into the block to find out which device is it. Could you...
  7. jluhzw

    stability simulation setup for Bandgap..

    I will do the tranisent simulation to test if it is stable when power on. Please take attention to the startup with different rate of power on.
  8. jluhzw

    Layout guidelines for best matching in analog circuits

    analog layout matching Hi There are too many document abaout layout match. First, you can refer to the Alan Hasstings' book "The Art of Analog Layout" This is most famous book about analog layout. Then you can also refer to the following material.
  9. jluhzw

    i need your help in temperature sensor design.

    Please take advantage of the comparator for comparing the bipolar Vbe( or Veb) with the voltage reference. Generally, the bipolar Vbe has a negative temperature coefficient, so when the temperature rise ,this voltage will go down.
  10. jluhzw

    small signal model for current mode buck

    Generally, we can't model the current mode buck by hspice. Some other tools can be used, such as simulink and Simetrix
  11. jluhzw

    small signal model for current mode buck

    this is a paper there is another paper
  12. jluhzw

    how to design diode current in BandGap?

    Generally, 3uA is OK. If the pnp bipolar is used, the main point is making the bipolar working in the region that its beta is constant when your current changes.
  13. jluhzw

    How to use .ALTER statement for models

    hspice alter As far as I know, you don't need using the " .dle lib....", if you want to change the model file, you can using the ".alter" and ".include ...." directly. You can also refer the manual of Hspice for more information.
  14. jluhzw

    current limit question in current mode buck converter ?

    Generally, the current limit is tested when it works in the low duty.And in low duty, the slope compensation is so small that you can ignore . I don't think you can acquire the current amp's gain from datasheet. Maybe what you interest in is the transconductance of the current sense.
  15. jluhzw

    Help me design a bandgap voltage reference

    Bandgap Voltage. Why don't you search papers in this site? There are many papers about lower voltage supply for the the bandgap. You can find some useful papers. Good luck!

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