Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I read lots of patents about clock recovery from Manchester codes. They all use delay techniques to delay the Manchester codes by 1/3, or 1/4, or 3/4 bit period. However, they did not mention what is this delay circuits and how to realize them. Could anyone tell me what circuit or element to...
low pass filter with differential input
I designed a low pass filter. It has a PMOS bias at the top, a PMOS input differential pair and a NMOS current mirror as an active load. Then connect the output to the negative input form a unity negative feedback. Finally a capacitor is connected to the...
low offset integrator
I designed an integrator, it is actually a low pass filter, a simple one stage differential amplifier with one terminal input short to the output and connected to a capacitor. In this case, the input is a signal, the output would be the input average voltage. All the...
I want to design edge triggered flip flops, such as a D flip flop. I found that there are two main topologies about edge triggered flip flop designs. One is master-slave flip flop. The other is to use a clock pulse train to clock the level triggered flip flops. Obviously, the second choice is...
I designed a very simple comparator, actually it is just a CMOS differential amplifier. I put a single comparator on the chip. The measurement showed that the offset is about 10mV and it can detect at least 15mVpp of 10kHz signal.
I used this comparator in one system. But this comparator...
I used Dracula to run DRC. The resolution and grid value defined in Dracula rule file is 1nm. I had no DRC errors. But someone used Calibre to check DRC and got large number of errors, which is offgrid. They said that the correct manufacturing grid is 10nm. The only way to get rid of this error...
Thank for your suggestions.
we did contact the corresponding party who supply the IC service to us. They don't provide bond ring and pad layout. Anyway, we have found a way to make the pad.
I find another problem regarding to the UMC 0.25u process, that is, I cannot draw the metal slot...
I use Dracula to run LVS. In the final .lvs result file. I got such warning.
POWER NODE IS NOT SPECIFIED
GROUND NODE IS NOT SPECIFIED
*/W* WARNING: NO POWER ON LAYOUT SIDE
*/W* WARNING: THEN THE POWER NODE MAY BE ASSIGNED DIFFERENT SCHEMATIC NAME.
*/W* WARNING: NO GROUND ON LAYOUT SIDE...
Dracula errors
When I use PDRACULA to compile the DRC rule files. I got plenty of errors.
**Error : LAYER ME1 HAS NOT BEEN DEFINE YET
......
The dracula drc file is obtained from IC company. I only need to set PRIMARY, INDISK, OUTDISK, PRINTFILE, right? how come I got some layers not defined?
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
